51>> Cyclic Redundancy Code CRC

Valid information group polynomial to encode: M (x)

Generating a polynomial (polynomial that produces a check code): G (x)

Remainder polynomial: R (x)

Quotient: Q (x)

The polynomial is generated four times, so a polynomial divided by the formula to generate the polynomial is definitely three times, so add four bits 0000.

The choice of generating polynomial is chosen by practical application, to meet certain requirements.

R (x) is the R-order, and R 0 (R (x) has r + 1 bits) after M (x).

M (x) *x^k = Q (x) *g (x) + R (x)

Modulo 2 operation

CRC code is a check code based on modulo 2 operation to establish coding law. Modulo 2 operations are characterized by operations that do not take into account rounding and borrow. The law is as follows:

1, modulo 2 plus and modulo 2 minus the result is equal, namely: 0 +/-1 = 1, 0 +/-0 = 0, 1 +/-0 = 1, 1 +/-1 = 0. Two of the same number of modulo 2 and constant is 0.

2, the modulus 2 is by the mold 2 and the sum of the partial product. (similar to decimal multiplication)

3, modulo 2 in addition to die 2 to reduce the partial remainder. Each vendor should reduce a portion of the remainder by one person. The principle of Shang Shang is: When the first part of the remainder is 1 o'clock, Shang Shang 1; When the first part of the remainder is 0 o'clock, Shang 0. When the number of bits of a partial remainder is less than the number of bits of the divisor, the remainder is the last remainder.

               1 1 1 0
────────
1 0 1 1)1 1 0 0 1 0 0
          -1 0 1 1
             ──────
               1 1 1 1
           -1 0 1 1
              ──────
                 1 0 0 0
             -1 0 1 1
                ──────
                   0 1 1 0
               -0 0 0 0
                  ──────
                     1 1 0

such as M (x) =1100

G (x) =1011

With 1100000 divided by 1011, the CRC code is 1100010.

Valid information is 4 bits, check bit is 3 bit, so there is called (7,4) code.

Check method:

The received loop check code is removed with the agreed-upon generation polynomial g (x), and if there is no error, the remainder should be 0; If an error occurs, the remainder is not 0, and the difference is the corresponding remainder. After adding 0 to the remainder, the remainder will be cycled in a certain sequence (the origin of the cyclic code).

For specific reference: http://bbs.csdn.net/topics/50365367

Here are the notes extracted from this site:

The CRC code is encoded by dividing the binary data (x) to be sent by the generation of the polynomial g (x) and the last remainder as the CRC check code. The following steps are implemented:
(1) The data block to be sent is the M-bit binary polynomial t (x), resulting in a polynomial of R-order g (x). At the end of the block, add R 0, the length of the data block is increased to m+r bit, and the corresponding binary polynomial is.
(2) The binary polynomial y (x) with the remainder as the order r-1 is obtained by the generation of the polynomial g (x). This binary polynomial y (x) is the CRC code that generates the polynomial g (x) encoded by T (x).
(3) Subtract Y (x) in the way of modulo 2 and get the binary polynomial. Is the string to be sent that contains the CRC check code.
From the CRC encoding rules can be seen, CRC encoding is actually the generation of M-bit binary polynomial T (x) is converted to a m+r binary polynomial can be eliminated by G (X), so the decoding can be used to remove the received data g (x), if the residual bit zero, it means that the transfer process without errors If the remainder is not zero, there must be an error in the transfer process. Many of the CRC's hardware decoding circuitry is done in this way for error detection. At the same time can be seen as a combination of T (x) and CRC checksum, so the decoding will receive the binary data removed from the tail of R-bit data, the original data is obtained.
In order to understand the coding process of CRC code more clearly, a simple example is used to illustrate the coding process of CRC code. Since the encoding process for CRC-32, CRC-16, CCITT, and CRC-4 is basically consistent, only the number of bits and the resulting polynomial are different. For the sake of simplicity, a CRC-4 coding example is used to illustrate the CRC encoding process.
Set the data to be sent T (x) is a 12-bit binary data 100100011100;crc-4 the resulting polynomial is g (x) =, the Order of R is 4, or 10011. First add 4 0 components at the end of T (x), and the data block becomes 1001000111000000. Then use g (x) to remove, without the operator is how much, only need to ask for the remainder of y (x). The following table shows the division process.
Divide the number of times/g (x)/result remainder
0 1 001000111000000100111000000
1 0011
0 000100111000000
1 1 00111000000 1000000
1 0011
0 00001000000
2 1 0000001100
1 0011
0 001100

As can be seen from the table above, CRC coding is actually a cyclic shift of the modulo 2 operation. For CRC-4, we assume that there is a 5 bits register, through repeated shifts and the division of the CRC, then eventually the value in this register is removed the highest one is the remainder we require. So the above steps can be described in the following process:
Reg is a 5 bits register
Set the value in reg to 0.
Add the original data after the R 0.
While (data is not finished processing)
Begin
If (reg first is 1)
Reg = Reg XOR 0011.
Move the value in Reg to the left one bit, and read a new data into the register's 0 bit position.
End
The following four bits of Reg are the remainder we require.
This algorithm is simple and easy to implement, and can be applied to the G (x) of any length generating polynomial. Can be used if the data sent is not long. However, if the data block is very long, this method is not suitable. It can handle only one data at a time and is inefficient. To improve processing efficiency, 4-bit, 8-bit, 16-bit, 32-bit can be processed at one time. Because the structure of the processor basically supports 8-bit data processing, it is more appropriate to handle 8 bits at a time.
In order to have an intuitive understanding of the optimized algorithm, first the above algorithm to understand a different angle. In the example above, the coding process can be thought of as follows:
Since only the remainder is required, we only look at the last four digits. Constructs a four-bit register Reg, the initial value is 0, the data is moved into REG0 (0 bits of Reg) in turn, and the data of REG3 is moved out of Reg. The above algorithm can be known that only if the data moved out is 1 o'clock, Reg and G (x) for the XOR operation, the data moved out of 0 o'clock, Reg does not with the G (X) XOR operation, equivalent and 0000 for XOR operation. That is, Reg and what data is determined by the XOR move out of the data. Because there is only one bit, there is a choice. The above algorithm can be described as follows,
Reg is a 4 bits register
Initialize t[]={0011,0000}
Set the value in reg to 0.
Add the original data after the R 0.
While (data is not finished processing)
Begin
Move the value in Reg to the left one bit, and read a new data into the register's 0 bit position.
Reg = Reg XOR t[moved out of the bit]
End
The above algorithm is processed in bits, and the above algorithm can be extended to 8 bits, that is, the processing in byte, that is, CRC-32. Constructs a register of four byte Reg, the initial value is 0x00000000, the data is moved into reg0 (reg 0 bytes, the following similar), while the REG3 data is moved out of Reg. By analogy with the algorithm above, the data bytes moved determine the XOR of the data. Since there are 8 bit, there is a choice. The above algorithm can be described as follows:
Reg is a 4 byte register
Initialize t[]={...} Total = 256 items
Set the value in reg to 0.
Add r/8 0 Bytes after the original data.
While (data is not finished processing)
Begin
Move the value in Reg to the left one byte, and read into a new byte and place it in the No. 0 byte of Reg.
Reg = Reg XOR t[moved out of bytes]
End
The basis of the algorithm is related to the character of polynomial division. If a M-bit polynomial t (x) is divided by a R-order to generate a polynomial g (x), each bit (0=<K<M) is presented, and after less than R 0, the sum of G (x) is removed separately, resulting in the remainder bit. The result is that T (x) is the remainder obtained by generating a polynomial g (x). For CRC-32, you can add each byte after 32 0 after the operation with the generation of polynomial, to get the remainder and this byte unique correspondence, the remainder is the above algorithm species t[] value, because a byte has 8 bits, so t[] total = 256 items. The polynomial operation properties can be found in reference [1]. This algorithm deals with one byte at a time, and the processing speed is greatly improved by the table-checking method, so it is used for most applications.


Excerpt from: Algorithm analysis and program implementation of cyclic redundancy check CRC
Liu Dong, School of Computer and Communication engineering, Southwest Jiaotong University

51>> Cyclic Redundancy Code CRC