6.4 Control signals for the command to be stored

The computer consists of a control signal of 6 single-cycle processor 6.4 visit instruction

For the instruction system such as MIPS, the operation instruction is not directly accessible to the memory, so we also need to design a separate access instruction, to complete the data transfer between the register and the memory. In this section, let's take a look at how this type of visit instruction generates a control signal.

For the processor we are going to implement, the fetch instruction is an I-type instruction, one is load and one is the store. We analyze them separately.

For the load directive. First of all, of course, also refers to, and then according to the address of the operation, access to the data memory, and the read out of the content to write to the register specified by the RT, and finally, the update PC register. The first and third steps are the same as the operation instructions. Here we will only explain the second step of the relevant operation.

This is our data path, and if the current Ifu is retrieving a load command, how will these control signals be set? First, the address of the next instruction should still be in the pc+4 way. Then we look at this side of the register heap, both RS and RT are fixed connected to the corresponding bit field of the instruction encoding, so the BusA and Busb are the contents of the registers specified by RS and RT, respectively.

But we should note that for this instruction, we want to calculate the addition of the contents of the RS register and the symbol extension of the immediate number. Therefore, for the source of the second operand of the ALU, we should select Channel 1 through this selector (ALUSRC), and set the extended part as the function of symbol extension (extop= "sign"). In this way, the 16-bit immediate number in the instruction bit field is signed and eventually connected to the second input of the ALU, and the control signal we send to the ALU is set to the addition operation (aluctr= "ADD"). In this way, the ALU completes the operation of the address and sends the address signal to the address input (ADR) of the data memory. It is also important to note that the signal on the BUSB is also connected to the data memory input (data in), although we do not need it, but this signal will still send the contents of the register specified by RT. So we need to set the data memory write enable signal (MEMWR) to set it to 0, to ensure that the contents of the data memory will not change. Then we look at the last of this selector, the two inputs of this selector, one is the result of the ALU operation, is the address to be visited, and the other is the data from the data memory, read out. So for this instruction, we obviously want to send the latter to the register heap. So, for this multi-selector, we need to set its selection signal to 1 (memtoreg=1) so that we can transfer the output of the data memory to the data input (BUSW) of the Register heap,
And since we are going to write the registers specified by RT, we need to set the write enable signal for the register heap to be valid (regwr=1) and set the source of the write register number to RT (regdst=0).

Thus, when the next clock rising edge arrives, the contents of the data memory output will be written to the register specified by RT, and the contents of the PC register will be updated to pc+4 on the same rising edge of the clock, which is what the load instructions do.

Then we look at the store directive, and the store directive is divided into three steps, as well as the second step.

For the store instruction, we also need to add the contents of the RS register and the symbol extension of the immediate number, and use this as an address to access the data memory, but not read it, but write it. So, in correspondence to the data path, we directly marked the valid signals for the store instruction. So how do these control signals be set? Then you might as well think about it, and we'll go over it quickly. For Ifu, we want to choose the address of the next instruction, is still pc+4 (npc_sel= "+4"), we want to choose the input of the ALU data, now we select the immediate number of the symbol extension (extop= "sign"; Alusrc=1), and for the ALU, we still have to choose the operation type of addition (aluctr= "ADD"). The result of the ALU operation is still an address, which is sent to the data memory. But unlike before, this instruction completes the write operation to the data memory. So, here we're going to set the write enable signal for the data memory to be valid (memwr=1). Thus, on the rising edge of the next clock, the data memory will sample the signal from its data input, but what is the signal at this input? We can take a look at the fact that it is connected to the BUSB, and the BUSB is the contents of the register specified by the RT signal. Therefore, when the next clock rising edge arrives, the datastore will select the corresponding storage unit according to the ALU-calculated address (ADR), and sample the contents from the RT register to save it to the corresponding storage unit. For the store directive, it does the main thing it needs to do, but for this data path, we have to set the rest of the control signals intact.

Let's look at the selector in the back because we don't need to rewrite the contents of the register heap for the store instruction, so no matter which path you choose, it doesn't make sense. Here we set the control signal, either 0 or 1, using X to mark (memtoreg=x). That way, the selector will always pick up a set of signals that will eventually be sent to the data input of the Register heap. However, we only need to set the write enable signal for the register heap to be invalid (regwr=0), and the contents of the register heap will not change when the clock rising edge arrives. Because of this, the register number to be written, whether set to RB or RT (REGDST=X), is also possible.

This is the method of setting the control signal for the store instruction.

Now that we have mastered how the access instructions generate the control signals, plus the previous operational instructions, we can write programs that allow the computer to do the corresponding tasks. However, if we want to write a more powerful program, it is not enough for the operation instruction and the fetch instruction, we also need to change the branch instruction of the program flow. This, we continue the analysis in the next section.

6.4 Control signals for the command to be stored