68013 power on "Unknown Device"

A 68013 minimum system bothered me for one weeks. Plug in the upper computer to identify the "unknown device." The measured reset is high and the crystal oscillator is also up. But the CPLD on the board can download and work normally. Later found to d+d-spray flux after re-welding, the host can be identified, but after a few minutes and then die. Until the 28th PM problem finally solved, the original is Seihan problem, reserved foot through 10K pull down after no grounding, the exact said is I draw the board when the ground, but the board made to not connect. I checked the other grounding pins, and several were not connected. The problem finally found, after the flight line plug in USB, finally prompted to find. This board is really killing me.

Summarize:

Check Start:

1.d+,d-, no mistake.

2.reserved, via 10k pull-down

3.EA, via 10k pull-down, but connected to one of the FPGA leg, set to output 0 (128 feet)

4.wakeup, through 10k pull (I don't use it here, I should be able to do it regardless of the foot)

5.clkout with 12m clock output

6.reset for high

When an unrecognized USB device appears, the most likely problem is whether the reserved pin has a pull. This is the key, do not underestimate this retention pin, directly lead to the USB device can be recognized, of course, if the other USB configuration pins are correctly set, including RESET,CLK,I2C SCL,SDA, all the normal appearance will be cy68013--eeprom missing.

When an unrecognized USB device appears, the most likely problem is whether the reserved pin has a pull. This is the key, do not underestimate this retention pin, directly lead to the USB device can be recognized, of course, if the other USB configuration pins are correctly set, including RESET,CLK,I2C SCL,SDA, all the normal appearance will be cy68013--eeprom missing.

Check if the clkout output is 12Mhz, which is the default after power-on, IFCLK should have no output.

Now you can open the device with controlpannal and the configuration interface will appear.

Note that the official belt of the first example of development, but in fact, the sample directory of the hex file can not be used, you need to recompile, including re-set the new project, such as re-down (bulkloop,bulksrc This example can) will be renum, re-device enumeration, Tip Find a new device Cypress sample device. In fact, 2 ID changed, the registration table has the corresponding options, and the development of PCI almost.

On-chip RAM access and endpoint settings specific reference Datasheet,ram equivalent to Fifobuf, but because of the existence of a double buffer, the use of Bulk/trans will occur when the point 2 appears 2 sets of data, the other endpoint in Access must be guaranteed length greater than EPXBCH <<8+EPXBCL, otherwise the system cannot be accessed.

On the question of the Bulkloop example, at least in my machine, there is a problem, that is, Keil compilation will be in the extautodat1 here to warn, if forced down the program, at the end of the data loop is not effective, prompted for unresovled extenal Symbol, I didn't even start to figure out why the other registers don't warn. Finally, the reason is that the EXTAUTODAT1 variable name has a problem, it is shortened, the problem is solved.

After several debugging cy7c68013 board, I summed up a few experience for debugging 68013 or trying to use the chip friend reference, also welcome to discuss together. The USB chip of the
Cypress Company has the features of simple development, complete documentation and examples, the driver does not write its own characteristics, very suitable for the development cycle of the use of tight.
for 68013 of its peripheral circuit can mainly refer to the circuit diagram in the development package, if you do not buy can go to the company website up and down.
I am using a 56 pin because it has been completely able to meet the requirements of general simple data transmission, its key pins have ifclk,wakeup,reset,d+,d-and power, ground. As long as they are right, the host can find the chip and identify it.
Ifclk, in general, we use the internal USB clock, it can be pulled through a large resistor to 3.3V. Of course, you can also receive a CPLD or FPGA, if you want to use an external clock, but note that it can only connect 5-48mhz clock. Therefore, in the use of Speed-adjustable FIFO read and write, there may be a small adjustable range of problems, which can be resolved by synchronous and asynchronous, at the time of synchronization it is 5-48mhz, when asynchronous X-20mhz (where x can be very small), In our project, we implemented a read/write FIFO of 200khz to 48mhz.
Wakeup, used to wake up the sleeping USB, generally we also use 100k resistor to pull to 3.3v. It is only used when you are very careful about power consumption.
Reset, Reset, eliminates the hassle of repeatedly plugging the device, but only if you are using a bus-powered mode. Be aware that when reset is grounded, there is also a large resistor between the 3.3v to avoid direct power-to-ground connection.
D+,d-is the data cable that communicates with the host, when the USB device is plugged into the host, d+ and d have a pressure difference, the host will find peripherals, demand pid and vid, load the corresponding driver. There may be two problems: 1, the host can not find peripherals 2, the host may find peripherals but not recognized, on the USB icon is a question mark. In the first case is mainly d+ and D-problem, because as long as the 4 cable to ensure that the interface is vcc,gnd,d+,d-as required, even if there is no peripheral, the host can also detect the peripheral, so if not detected, it is likely that wired to reverse; in the second case, the reason is much more, a,d+, D-Line is too long, too thin, too many corners so that the data transmission error, VID and PID can not be transmitted correctly, at this time may appear sometimes recognizable, sometimes not recognized. b, the USB chip is not working properly due to several pins not being picked up on the above