74 series Chip Pin chart data Daquan

Inverter driver ls04 ls05 ls06 ls07 ls125 ls240 ls244 ls245

And door and non-door ls00 ls08 ls10 ls11 ls20 ls21 ls27 ls30 ls38

Or door or non-door and non-door ls02 ls32 ls51 ls64 ls65

Cross-or gate comparator ls86

Decoder ls138 ls139

Register ls74 ls175 ls373

Inverter:

VCC 6a 6y 5A 5y 4A 4Y six non-door 74ls04
Commandid-parallel six non-door (OC gate) 74ls05
_ │ 14 13 12 11 10 9 8 │ six non-door (OC high voltage output) 74ls06
Y = a) │
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
1A 1y 2a 2y 3A 3Y Gnd

Drive:
VCC 6a 6y 5A 5y 4A 4Y
Zookeeper-acceleration-Acceleration
│ 14 13 12 11 10 9 8 │
Y = a) │ six Drivers (OC high voltage output) 74ls07
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
1A 1y 2a 2y 3A 3Y Gnd

VCC-4c 4A 4Y-3C 3A 3Y
Zookeeper-acceleration-Acceleration
_ │ 14 13 12 11 10 9 8 │
Y = a + C) │ four bus three-state gate 74ls125
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
-1C 1A 1y-2C 2a 2y Gnd

VCC-G B1 B2 B3 B4 B8 B6 B7 B8
Commandid-parallel-serial-Parallel Balanced 8-bit bus driver 74ls245
│ 20 19 18 17 16 15 14 13 12 11 │
) │ Dir = 1 A => B
│ 1 2 3 4 5 6 7 8 9 10 │ dir = 0 B =>
Zookeeper-acceleration Acceleration
Dir A1 A2 A3 A4 A5 A6 A7 A8 Gnd

Top non-door, drive and door, non-door or door, or non-door exclusive or door, comparator decoder register

Positive logic and door, and non-door:

VCC 4B 4A 4Y 3B 3A 3Y
Zookeeper-acceleration-Acceleration
│ 14 13 12 11 10 9 8 │
Y = AB) │ 2 input four positive and door 74ls08
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
1A 1B 1y 2a 2B 2y Gnd

VCC 4B 4A 4Y 3B 3A 3Y
Zookeeper-acceleration-Acceleration
_ │ 14 13 12 11 10 9 8 │
Y = AB) │ 2 input four positive and non-gate 74ls00
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
1A 1B 1y 2a 2B 2y Gnd

VCC 1C 1y 3C 3B 3A 3Y
Zookeeper-acceleration-Acceleration
___ │ 14 13 12 11 10 9 8 │
Y = ABC) │ 3 input three positive and non-gate 74ls10
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
1A 1B 2a 2B 2C 2y Gnd

VCC H G Y
Zookeeper-acceleration-Acceleration
│ 14 13 12 11 10 9 8 │
) │ 8-entry and non-gate 74ls30
│ 1 2 3 4 5 6 7 │ ________
Required bytes-modified-since-modified using Y = abcdefgh
A B C D E F Gnd

Top non-door, drive and door, non-door or door, or non-door exclusive or door, comparator decoder register

Positive logic or gate, or non-Gate:

VCC 4B 4A 4Y 3B 3A 3Y
Please choose-allow-Deny deny 2 enter four or gate 74ls32
│ 14 13 12 11 10 9 8 │
) │ Y = a + B
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
1A 1B 1y 2a 2B 2y Gnd

VCC 4Y 4B 4A 3Y 3B 3A
Please choose-Internal-external-Internal limit 2 input four or non-gate 74ls02
│ 14 13 12 11 10 9 8 │ ___
) │ Y = a + B
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
1y 1A 1B 2y 2a 2B Gnd

VCC 2y 2B 2a 2D 2E 1f
Zookeeper-Internal-external-Internal dual-or non-door 74s51
│ 14 13 12 11 10 9 8 │ _____
) │ 2y = AB + de
│ 1 2 3 4 5 6 7 │ _______
└ ┬-┬ ┘ 1y = ABC + def
1y 1A 1B 1C 1D 1E Gnd

Vcc d c B k J y
┌ ┴--┴ ┐ 4-2-3-2 and/or non-gate 74s64 74s65 (OC gate)
│ 14 13 12 11 10 9 8 │ ______________
) │ Y = ABCD + EF + Ghi + jk
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
A e f g h I Gnd

Top non-door, drive and door, non-door or door, or non-door exclusive or door, comparator decoder register

2. Enter the four exclusive OR gate 74ls86.

VCC 4B 4A 4Y 3Y 3B 3A
Zookeeper-acceleration-Acceleration
│ 14 13 12 11 10 9 8 │
) │ __
│ 1 2 3 4 5 6 7 │ y = AB + AB
Zookeeper-acceleration-Acceleration
1A 1B 1y 2y 2a 2B Gnd

8*2 input comparator 74ls688

_
VCC y B8 A8 B7 A7 B6 A6 B5 A5
┌ ┴-┴ ┐ 8*2 input comparator 74ls688
│ 20 19 18 17 16 15 14 13 12 11 │
) │
│ 1 2 3 4 5 6 7 8 9 10 │
Zookeeper-acceleration Acceleration
Ce A1 B1 A2 B2 A3 B3 A4 B4 Gnd
_
Y = A1 ⊙ B1 + A2 ⊙ B2 + A3 ⊙ B3 + A4 ⊙ B4 + A5 ⊙ B5 + A6 ⊙ B6 + A7 ⊙ B7 + A8 ⊙ B8

Top non-door, drive and door, non-door or door, or non-door exclusive or door, comparator decoder register

3-8 decoder 74ls138
VCC-y0-Y1-Y2-Y3-Y4-Y5-y6 ________________
Required bytes-modified-since policy0 = a B c Y1 = a B y2 = a B c Y3 = A B C
│ 16 15 14 13 12 11 10 9 │
) │ ____________
│ 1 2 3 4 5 6 7 8 │ Y4 = a B c Y5 = a B c y6 = a B c y7 = A B C
Zookeeper-acceleration-Acceleration
A B C-CS0-CS1 CS2-y7 Gnd

74ls139 dual-2-4 Decoder
VCC-2g 2a 2b-y0-Y1-Y2-Y3 ________________
Zookeeper-Zookeeper Y0 = 2a 2B Y1 = 2a 2B y2 = 2a 2B Y3 = 2a 2B
│ 16 15 14 13 12 11 10 9 │
) │ ________________
│ 1 2 3 4 5 6 7 8 │ Y0 = 1a 1B Y1 = 1a 1B y2 = 1a 1B Y3 = 1a 1b
Zookeeper-acceleration-Acceleration
-1g 1A 1b-y0-Y1-Y2-Y3 Gnd

8*2 input comparator 74ls688

_
VCC y B8 A8 B7 A7 B6 A6 B5 A5
┌ ┴-┴ ┐ 8*2 input comparator 74ls688
│ 20 19 18 17 16 15 14 13 12 11 │
) │
│ 1 2 3 4 5 6 7 8 9 10 │
Zookeeper-acceleration Acceleration
Ce A1 B1 A2 B2 A3 B3 A4 B4 Gnd
_
Y = A1 ⊙ B1 + A2 ⊙ B2 + A3 ⊙ B3 + A4 ⊙ B4 + A5 ⊙ B5 + A6 ⊙ B6 + A7 ⊙ B7 + A8 ⊙ B8

Register:
VCC 2Cr 2D 2CK 2st 2q-2q
Commandid-train dual-D Trigger 74ls74
│ 14 13 12 11 10 9 8 │
) │
│ 1 2 3 4 5 6 7 │
Zookeeper-acceleration-Acceleration
1cr 1D 1ck 1st 1q-1q Gnd

VCC 8q 8d 7d 7q 6q 6D 5d 5q ale
┌ ┴-Audio-extract memory 8-bit latches 74LS373
│ 20 19 18 17 16 15 14 13 12 11 │
) │
│ 1 2 3 4 5 6 7 8 9 10 │
Zookeeper-acceleration Acceleration
-Oe 1q 1D 2D 2q 3q 3D 4D 4Q Gnd

And so on.

 

 

 

The following describes the commonly used 74 chips, so that you may encounter queries in the circuit.
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Model content
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74ls00 2 input four and non-gate
74ls01 2 input 4 and non-gate (OC)
74ls02 2 input four or not
74ls03 2 input 4 and non-gate (OC)
74ls04
74ls05 6 invert (OC)
74ls06 six high-voltage output reverse-phase buffer/drive (OC, 30 V)
74ls07 high-voltage output buffer/drive (OC, 30 V)
74ls08 2 input 4 and door
74ls09 2 input 4 and door (OC)
74ls10 3 input three and non-gate
74ls11 3 input 3 and door
74ls12 3 input 3 and non-gate (OC)
74ls13 4 input dual-and non-gate (triggered by sstables)
74ls14 six-phase generator (triggered by s)
74ls15 3 input 3 and gate (OC)
74ls16 six high-voltage output reverse-phase buffer/drive (OC, 15 V)
74ls17 six high-voltage output buffer/drive (OC, 15 V)
74ls18 4 input dual-and non-gate (triggered by sstables)
74ls19 six-phase generator (triggered by s)
74ls20 4 input dual-and non-gate
74ls21 4 input dual and door
74ls22 4 input dual-and non-gate (OC)
74ls23 double scalable input or non-gate
74ls24 2 input 4 and off-gate)
74ls25 4 input dual or non-gate (available)
74ls26 2 input 4-level interface and non-buffer (OC, 15 V)
74ls27 3 input three or not
74ls28 2 input 4 or non-Buffer
74ls30 8 Input and non-gate
74ls31 delay Circuit
74ls32 2 input four or gate
74ls33 2 input 4 or non-buffer (open collector output)
74ls34 six Buffers
74ls35 six buffers (OC)
74ls36 2 input four or non-gate (available)
74ls37 2 input four and non-Buffer
74ls38 2 input 4 or non-buffer (open collector output)
74ls39 2 input 4 or non-buffer (open collector output)
74ls40 4 input dual and non-Buffer
74ls41 BCD-decimal counter
74ls42 4-10-line Decoder (BCD input)
74ls43 4-10-line Decoder (additional 3 code input)
74ls44 4-10-line Decoder (remainder 3 Gloria code input)
74ls45 BCD-decimal Decoder/drive
74ls46 BCD-seven-segment Decoder/driver
74ls47 BCD-seven-segment Decoder/driver
74ls48 BCD-seven-segment Decoder/driver
74ls49 BCD-seven-segment Decoder/drive (OC)
74ls50 dual two-way 2-2 input and non-door (one Scalable)
74ls51 dual-circuit 2-2 input and non-door
74ls51 2-3 input, 2-2 input, or non-gate
74ls52 four-way 2-3-2-2 input and/or gate (Scalable)
74ls53 four-way 2-2-2 input and/or non-door (Scalable)
74ls53 four-way 2-3-2 input and/or non-door (Scalable)
74ls54 4-way 2-2-2 input and non-gate
74ls54 four-way 2-3-3-2 input and/or non-gate
74ls54 four-way 2-3-2 input and non-gate
74ls55 two-way 4-4 input and non-gate (Scalable)
74ls60 dual-Quad input and extension
74ls61 3 input and extension
74ls62 quad-path 2-3-3-2 input and or extended
74ls63 six-current read interface door
74ls64 quad-4-2-3-2 input and non-gate
74ls65 quad-4-2-3-2 input and non-gate (OC)
74ls70 and JK trigger on the rising edge of the door Input
74ls71 and input r-s Master/Slave triggers
74ls72 and door input Master/Slave JK trigger
74ls73 dual J-K trigger (with clearing end)
74ls74 positive edge trigger double D trigger (with preset side and clear side)
74ls75 4-bit bistability latches
74ls76 dual J-K trigger (with preset side and clear side)
74ls77 4-bit bistability latches
74ls78 dual J-K trigger (with preset end, public clearing end and public clock end)
74ls80 gate Controller
74ls81 16-bit random access memory
74ls82 two-bit binary full processors (fast carry)
74ls83 4-bit binary full processors (fast carry)
74ls84 16-bit random access memory
74ls85 4-bit digital comparator
74ls86 2 input four exclusive OR gate
74ls87 binary original code/reverse code/OI Unit
74ls89 64-bit read/write memory
74ls90 decimal counter
74ls91 eight-displacement register
74ls92 12-frequency counter (2-frequency and 6-frequency)
74ls93 4-bit binary counter
74ls94 4-position register (asynchronous)
74ls95 4 displacement register (parallel Io)
74ls96 5 displacement register
74ls97 six-bit binary rate Multiplier
74ls100 eight-bit bistability latches
74ls103 trigger dual J-K Master/Slave trigger (with cleanup side)
74ls106 trigger dual J-K Master/Slave trigger along the negative edge (with preset, clear, clock)
74ls107 dual J-K Master/Slave trigger (with clearing end)
74ls108 dual J-K Master/Slave trigger (with preset, clear, clock)
74ls109 dual J-K trigger (with set bit, clear, trigger)
74ls110 and door Input j-K Master/Slave trigger (with lock)
74ls111 dual J-K Master/Slave trigger (with data lock)
74ls112 negative edge trigger double J-K trigger (with preset side and clear side)
74ls113 trigger dual J-K trigger with a negative edge (with preset side)
74ls114 dual J-K trigger (with preset end, total clearing end and clock end)
74ls116 dual-four-bit latches
74ls120 dual pulse synchronization/driver
74ls121 monostable trigger (triggered by Schmidt)
74ls122 can trigger a single-Steady-state multi-harmonic oscillator (with cleaning end)
74ls123 can trigger dual-monostable multi-Harmonic Oscillator
74ls125 four-bus buffer door (three-state output)
74ls126 four-bus buffer gate (three-state output)
74ls128 2 input four or non-linear drive
74ls131 3-8 Decoder
74ls132 2 input four and non-gate)
74ls000013 input and non-gate
74ls134 12 input and gate (three-state output)
74ls135 four exclusive or non-door
74ls136 2 input four exclusive OR gate (OC)
74ls137 select one lockdown Decoder/multi-channel Converter
74ls138-3-8 line Decoder/multi-channel Converter
74ls139 dual-2-4-wire Decoder/multi-channel Converter
74ls140 dual 4 input and non-linear drive
74ls141 BCD-decimal Decoder/drive
74ls142 counters/latches/Decoder/drive
74ls145 4-10 Decoder/driver
74ls147 10-4-wire priority encoder
74ls148 8-wire-3-wire octal Encoder
74ls150 16 select 1 data selector (reverse complement output)
74ls151 8 select 1 data selector (complementary output)
74ls152 8 select 1 data selector Multi-Channel Switch
74ls153 dual 4 select 1 data selector/multi-channel selector
74ls154 4-wire-16 Decoder
74ls155 dual-2-4 Decoder/distributor (Totem Pole Output)
74ls156 dual-2-4 Decoder/distributor (open collector output)
74ls157 4 2 select 1 data selector/multi-channel selector
74ls158 4 2 select 1 data selector (reverse output)
74ls160 preset BCD counters (asynchronously cleared)
74ls161 presets four-digit binary counters (and clears Asynchronization)
74ls162: preset BCD counters (asynchronously cleared)
74ls163 can Preset four-digit binary counters (and clear Asynchronization)
74ls164 8-bit parallel output serial shift register
74ls165 parallel input 8 displacement register (complement output)
74ls166 8 displacement register
74ls167 synchronous decimal rate Multiplier
74ls168 4-digit plus/minus synchronization counter (decimal)
74ls169 synchronous binary reversible counter
74ls170 4*4 register heap
74ls171 quad-D trigger (with clearing end)
74ls172 16-bit register heap
74ls173 4-bit D register (with clearing end)
74ls174 6 D Trigger
74ls175 four D Trigger
74ls176 decimal preset counter
74ls177 2-8-16 preset counters
74ls178 four-digit general shift register
74ls179 four-digit general shift register
74l81's nine-digit parity Generator/validator
74ls181 arithmetic logic unit/Function Generator
74ls182 advance Generator
74ls183 dual-reserved carry-All Processors
74ls184 BCD-binary Converter
74ls185 Binary-BCD Converter
74ls190 synchronous reversible counter (BCD, binary)
74ls191 synchronous reversible counter (BCD, binary)
74ls192 synchronous reversible counter (BCD, binary)
74ls193 synchronous reversible counter (BCD, binary)
74ls194 four-digit bidirectional universal shift register
74ls195 four-digit general shift register
74ls196 preset counters/latches
74ls197 preset counters/latches (Binary)
74ls198 eight-bit bidirectional shift register
74ls199 Octa displacement register
74ls210 2-5-10 hexadecimal counter
74ls213 2-n-10 mutable counter
74ls221 dual-stability trigger
74ls230 eight 3-state bus driver
74ls231 eight 3-state bus reverse drive
74ls240 eight buffers/line drive/line receiver (three-state output of anti-code)
74ls241 eight buffers/line Drivers/line receivers (original three-state output)
74ls242 eight buffers/wire drive/wire Receiver
74ls243 4 same-phase tri-state bus transceiver
74LS244 eight buffers/wire drive/wire Receiver
74ls245 eight bidirectional bus transceiver
74ls246 4-wire-7-segment decoding/drive (30 V)
74ls247 4-wire-7-segment decoding/drive (15 V)
74ls248 4-wire-seven-segment decoding/driver
74ls249 4-wire-seven-segment decoding/driver
74ls251 8 select 1 data selector (three-state output)
74ls253 dual-quad-select-1 data selector (three-state output)
74ls256 dual-four-bit addressable latches
74ls257 4 2 select 1 data selector (three-state output)
74ls258 4 2 select 1 data selector (three-state output of anti-code)
74ls259 8 addressable latches
74ls260 double 5 input or non-door
74ls261 4*2 parallel binary Multiplier
74ls265 four complementary output elements
74ls266 2 input four exclusive or non-gate (OC)
74ls270 2048-bit Rom (512-bit four-byte, OC)
74ls271 2048-bit Rom (256-bit octal node, OC)
74LS273 8 D Trigger
74ls274 4*4 parallel binary Multiplier
74ls275 seven-bit Wallace Tree Multiplier
74ls276 4 JK trigger
74ls278 four-bit cascade priority register
74ls279 quad-r latches
74ls280 9-bit odd/Even Parity Generator/Comparator
74ls281
74ls283 4-bit binary full Processors
74ls290 decimal counter
74ls291 32-bit programmable mode
74ls293 4-bit binary counter
74ls294 16-bit programmable mode
74ls295 four-digit bidirectional universal shift register
74ls298 quad-2 Input Multi-Channel converter (with select)
74ls299 eight-bit common shift register (three-state output)
74ls348 8-3 line priority encoder (three-state output)
74ls352 dual-quad-select 1 data selector/multi-channel Converter
74ls353 dual 4-1 line data selector (three-state output)
74ls354 8 Input Multi-Channel converter/data selector/register, three-state complement output
74ls355 8 Input Multi-Channel converter/data selector/register, three-state complement output
74ls356 8 Input Multi-Channel converter/data selector/register, three-state complement output
74ls357 8 Input Multi-Channel converter/data selector/register, three-state complement output
74ls365 6 bus driver
74ls366 6 reverse tri-state buffer/line drive
74ls367 six three-state buffer/wire drive in the Same Direction
74ls368 6 reverse tri-state buffer/line drive
74LS373 eight D latches
74LS374 eight D trigger (three-state same phase)
74ls375 4-bit bistability latches
74ls377 8 d trigger with enabling
74ls378 6 D Trigger
74ls379 four D Trigger
74ls381 arithmetic logic unit/Function Generator
74ls382 arithmetic logic unit/Function Generator
74ls384 8-bit * 1-bit complement Multiplier
74ls385 four-Serial Multiplier/Multiplier
74ls386 2 input four exclusive OR gate
74ls390 dual-decimal counter
74ls391 dual four-digit binary counter
74ls395 4-bit general shift register
74ls396 eight-bit storage register
74ls398 quad 2 Input Multi-Channel Switch (Dual Output)
74ls399 quad-2 Input Multi-Channel converter (with select)
74ls422 monostable trigger
74ls423 double single steady-state trigger
74ls440 quad-3 bus transceiver, open collector
74ls441 quad-3 bus transceiver, open collector
74ls442 quad-3 bus transceiver, three-state output
74ls443 quad-3 bus transceiver, three-state output
74ls444 quad-3 bus transceiver, three-state output
74ls445 BCD-decimal Decoder/drive, three-state output
74ls446 dual-bus transceiver with direction control
74ls448 quad-3 bus transceiver, three-state output
74ls449 dual-bus transceiver with direction control
74ls465 eight three-state line buffer
74ls466 eight-three-state reverse Buffer
74ls467 eight three-state line buffer
74ls468 eight three-state reverse Buffer
74ls490 dual-decimal counter
74ls540 eight-bit tri-state bus buffer (reverse)
74ls541 eight-bit tri-state bus Buffer
74ls589 input-locked merge-out shift register
74ls590 8-bit binary counter with output register
74ls591 8-bit binary counter with output register
74ls592 8-bit binary counter with output register
74ls593 8-bit binary counter with output register
74ls594 8-bit string with output lock into and out shift register
74ls595 8-bit output lock shift register
74ls596 8-bit string with output lock into and out shift register
74ls597 8-bit output lock shift register
74ls598 input-locked merge-out shift register
74ls599 8-bit string with output lock into and out shift register
74ls604 Dual 8-bit latches
74ls605 Dual 8-bit latches
74ls606 Dual 8-bit latches
74ls607 Dual 8-bit latches
74ls620 8-bit three-state bus transmission receiver (reverse phase)
74ls621 8-bit bus transceiver
74ls622 8-bit bus transceiver
74ls623 8-bit bus transceiver
74ls640 reverse-phase bus transceiver (three-state output)
74ls641 same-Phase 8 bus transceiver, open collector
74ls642 same-Phase 8 bus transceiver, open collector
74ls643 8-bit three-state bus transmission Receiver
74ls644 true-value inverted 8 bus transceiver, open collector
74ls645 tri-state eight-phase bus transceiver
74ls646 eight-bit bus transceiver, register
74ls647 eight-bit bus transceiver, register
74ls648 eight-bit bus transceiver, register
74ls649 eight-bit bus transceiver, register
74ls651 triplicate eight bus transceiver
74ls652 triplicate eight bus transceiver
74ls653 Reversed-Phase 8 bus transceiver, open collector
74ls654 same-Phase 8 bus transceiver, open collector
74ls668 4-Digit Synchronous addition/subtraction decimal counter
74ls669 binary reversible counter with a forward position
74ls670 4*4 register heap (three-state)
74ls671 four-digit merge with and out shift register with output Storage
74ls672 four-digit merge with and out shift register with output Storage
74ls673 16-bit parallel output memory, 16-Bit String-in-string out shift register
74ls674 16-bit Parallel Input Serial Output shift register
74ls681 4-bit Parallel binary Accumulators
74ls682 8-bit numeric Comparator)
74ls683 8-bit numeric comparator (open collector)
74ls684 8-bit numeric Comparator)
74ls685 8-bit numeric comparator (open collector)
74ls686 8-bit numeric Comparator)
74ls687 8-bit numeric comparator (open collector)
74ls688 8-bit digital comparator (OC output)
74ls689 8-bit digital comparator
74ls690 synchronous decimal counter/register (with number selection, three-state output, clear directly)
74ls691 counter/register (with Multiple conversions and three-state output)
74ls692 synchronous decimal counter (with preset input, synchronously cleared)
74ls693 counter/register (with Multiple conversions and three-state output)
74ls696 synchronous addition/subtraction decimal counter/register (with number selection, three-state output, directly clear)
74ls697 counter/register (with Multiple conversions and three-state output)
74ls698 counters/registers (with Multiple conversions and three-state output)
74ls699 counters/registers (with Multiple conversions and three-state output)
74ls716 programmable modulo n decimal counter
74ls718 programmable modulo n decimal counter