A complete set of practical Makefile reference templates

Article Title: a complete set of practical Makefile reference templates. Linux is a technology channel of the IT lab in China. Includes basic categories such as desktop applications, Linux system management, kernel research, embedded systems, and open source.
Recently, we often see people asking about makefile writing. Here is a complete example of an application system based on my experience for your reference.
　　
The application system directory structure is as follows:
Code:
　　
~ /Bin executable program directory
~ /Etc configuration file directory
~ /Inc header file directory
~ /Lib library file directory
~ /Log file directory
~ /Src source program file directory
~ /Src/lib Library source program directory
~ /Src/lib/LIB_1 library libLIB_1 source code directory
~ /Src/APP_A subsystem APP_A source program directory
~ /Src/APP_A/mod_a subsystem APP_A module mod_a source program directory
~ /. Profile
~ /Makefile
　　
　　
~ The content of the/makefile file is as follows:
Code:
　　
All:
@ MakeSubDir () {for DIR in 'ls | grep 'lib'; ls | grep-v 'lib''; do if [-d $ {DIR}]; then cd $ {DIR}; MakeSubDir; if [-f makefile-o-f Makefile]; then echo ""; pwd; make all; fi; cd ..; fi; done ;}; MakeSubDir
　　
Tar:
@ Tar-cf 'date when policyymm=d-w.hsf-m=s'.tar. profile 'ls | grep-v '.tar''
　　
　　
~ The content of the/src/lib/LIB_1/makefile file is as follows:
Code:
　　
ALL: INFO all
　　
BASEDIR = $ (HOME)
INC = $ (BASEDIR)/inc
LIB = $ (BASEDIR)/lib
　　
PRDNAME = $(LIB)/libLIB_1
　　
PRODUCT = $ (PRDNAME). a $ (PRDNAME). so
　　
OBJS = lib_rjf1.o LIB_1_f2.o
　　
AR = ar <特定平台ar可选参数>
CC = cc <特定平台cc可选参数>
　　
All: $ (PRODUCT)
　　
$ (PRDNAME). a: $ (OBJS)
@ Echo "Making $ @..."
@ $ (AR)-r $ @ $ (OBJS)
　　
$ (PRDNAME). so: $ (OBJS)
@ Echo "Making $ @..."
@ $ (CC)-G-o $ @ $ (OBJS)
　　
. C. o: *. h $ (INC)/*. h
@ Echo "Compiling $ <..."
@ $ (CC)-c-I $ (INC) $ <
　　
INFO:
@ Echo "make all-same with 'make' handle t this message"
@ Echo "make clear-remove object files"
@ Echo "make clean-remove all object and target files"
@ Echo ""
　　
Clear: FORCE
@ Rm-f *. o
　　
Clean: FORCE clear
@ Rm-f $ (PRODUCT)
　　
FORCE:
　　
　　
~ The content of the/src/APP_A/mod_a/makefile file is as follows:
Code:
　　
ALL: INFO all
　　
BASEDIR = $ (HOME)
INC = $ (BASEDIR)/inc
LIB = $ (BASEDIR)/lib
BIN = $ (BASEDIR)/bin
　　
MODULE = $ (BIN)/APP_A_mod_a
TESTER = APP_A_mod_a_t
PRODUCT = $ (SERVER) $ (TESTER)
　　
CC = cc <特定平台cc可选参数>
　　
All: $ (PRODUCT)
　　
$ (MODULE): APP_A_mod_a.o
@ Echo "Making $ @..."
@ $ (CC) $? -O $ @-L $(LIB)-lLIB_1
　　
APP_A_mod_a_t: APP_A_mod_a_t.o
@ Echo "Making $ @..."
@ $ (CC) $? -O $ @-L $(LIB)-lLIB_1
　　
. C. o: *. h $ (INC)/*. h
@ Echo "Compiling $ <..."
@ $ (CC)-c-I $ (INC) $ <
　　
INFO:
@ Echo "make all-same with 'make' handle t this message"
@ Echo "make clear-remove object files"
@ Echo "make clean-remove all object and target files"
@ Echo ""
　　
Clear: FORCE
@ Rm-f *. o
　　
Clean: FORCE clear
@ Rm-f $ (PRODUCT)
　　
FORCE:
　　
　　
Usage:
1. Use the 'make' command in the main directory to first create a function library and then create all the targets.
2. Use the 'Make tar 'command in the main directory to package the entire system. The generated file is named by date and time.
3. directly using the 'make' command in the lowest subdirectory will first give a usage prompt, and then create all the targets in the directory.
4. Use the 'Make all' command in the lowest-level subdirectory to directly create all targets in the directory without any prompts.
5. Use the 'Make clear' command in the lowest-level subdirectory to clear all. o files in this directory.
6. Use the 'Make clean' command in the lowest-level subdirectory to clear all. o files and all created targets in this directory.