A simple example of using makefile

A simple example of using makefile

Use an example to illustrate how to compile makefile.

Program source code:
// File: A. H
# Ifndef a_h
# Define a_h

Class {
Public:
A ();
~ A ();
Void F ();
};

# Endif // a_h

// File: A. cpp
# Include "A. H"
A: (){
}
A ::~ (){
}
Void A: F (){
}

// File: B. H
# Ifndef B _h
# Define B _h

Class B {
Public:
B ();
~ ();
Void g ();
};

# Endif // B _h

// File: B. cpp
# Include "B. H"
B: B (){
}
B ::~ B (){
}
Void B: G (){
}

// File: Main. cpp
# Include "A. H"
# Include "B. H"

Int main ()
{
A;
B;
B. G ();
Return 0;
}

The preceding source program should be organized in the most common way. Now write

A makefile file that allows the compiler to compile automatically.
The MAKEFILE file consists of one target-dependent command,

Generally, a command like this is written in two lines. The second line is usually
Is to compile the connection command. And start with the <tab> key at the beginning of the line, followed by the command.

The make program executes these commands one by one.

Second, the form of the target dependency command is

Target: Dependencies
<Tab> command ARGs

Now we need to understand what compilation commands are used. Because it is on Unix/Linux,

So it should be CC/GCC/g ++.

Make it clear that the final executable target program consists of all. cpp files.

The compiled. o file is composed together.

Now, we are writing the MAKEFILE file.

We assume that the name of the last generated executable target is exam.

# Comment, start with # (sharp)

Exam: Main. o a. o B. O
G ++ main. o a. o B. O-o exam
Main. O: Main. cpp A. h B. H
G ++-C main. cpp-O main. o
A. O: A. cpp a. h
G ++-c a. cpp-o a. o
B .o: B .cpp B .h
G ++-c B. cpp-o B. O
# Makefile end

Note that each command starts with the <tab> key.

After writing it, put it in the directory where the source file is located.

Then run

$ Make

The compilation command line you used is displayed.

Of course, macro variables can be used in makefile. This is at least easier to write.

First, we will introduce three special predefined macro variables.

$ @ Refers to the current target name (target)

$ ^ Indicates the entire list of dependent files (dependencies)

$ <Indicates the first item in the current file list.

As described above, a macro variable can be used to replace a file list.

So how can we reference these macro variables? Is to add the variable name with the symbol $.

Note: If the macro variable name contains more than one name, enclose $ (name) in parentheses ).

The format of macro variables is

Macro_name = string1 string2...

Here, string can be the file name or compiler parameter.

Now let's make some changes to the makefile.

# Makefile using macro variants

Objs = Main. o a. o B. O
Cc = g ++

Exam: $ (objs)
$ (CC) $ ^-o $ @
Main. O: Main. cpp A. h B. H
$ (CC)-C $ <-o $ @
A. O: A. cpp a. h
$ (CC)-C $ <-o $ @
B .o: B .cpp B .h
$ (CC)-C $ <-o $ @
# Makefile end

Basically, this is a commonly used makefile.

After compilation, many. O files are left. You can also clear them in makefile.
How can this problem be solved?
Add the following command at the end of the above file:

Clean:
Rm-f *. o

Then, run the command

$ Make clean

Success.

Let's explain the last command. Clean is just a target name,

You can also change it to another one, such as cleanup.

Then, the make clean command is used to allow the make program to accomplish the specified target.