About place:909 problem solving--DDR3 debug record

The following issues occur when debugging on the V6 chip using the MIG3.92 dual controller:

Place:909-Regional Clock Net"i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>"Cannot possibly be routed to Component "i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_ IOB/U_ODELAY_DM"(PlacedinchClock region"Clockregionp_x1y2"), since it isToo far away from source BUFR"I_MIGDOUBLEINTERFACE/C1_U_MEMC_UI_TOP/U_MEM_INTFC/PHY_TOP0/U_PHY_READ/U_PHY_RDCLK_GEN/GEN_LOOP_COL1.U_BUFR _rsync"(PlacedinchClock region"Clockregion_x1y4"). The situation is caused by user constraints,orThe complexity ofThe design. Constraining the components related toThe regional clock properly the tool toFind a solution. To debug your design withPartially routed results, please allowMap/placer toFinish the execution (by setting environmentvariableXil_par_debug_ioclkplacer to 1). Place:909-Regional Clock Net"i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>"Cannot possibly be routed to Component "i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[6].u_phy_dm_ IOB/U_ODELAY_DM"(PlacedinchClock region"Clockregionp_x1y2"), since it isToo far away from source BUFR"I_MIGDOUBLEINTERFACE/C1_U_MEMC_UI_TOP/U_MEM_INTFC/PHY_TOP0/U_PHY_READ/U_PHY_RDCLK_GEN/GEN_LOOP_COL1.U_BUFR _rsync"(PlacedinchClock region"Clockregion_x1y4"). The situation is caused by user constraints,orThe complexity ofThe design. Constraining the components related toThe regional clock properly the tool toFind a solution. To debug your design withPartially routed results, please allowMap/placer toFinish the execution (by setting environmentvariableXil_par_debug_ioclkplacer to 1). Place:909-Regional Clock Net"i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>"Cannot possibly be routed to Component "i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_ IOB/U_ODELAY_DM"(PlacedinchClock region"Clockregionp_x1y2"), since it isToo far away from source BUFR"I_MIGDOUBLEINTERFACE/C1_U_MEMC_UI_TOP/U_MEM_INTFC/PHY_TOP0/U_PHY_READ/U_PHY_RDCLK_GEN/GEN_LOOP_COL1.U_BUFR _rsync"(PlacedinchClock region"Clockregion_x1y4"). The situation is caused by user constraints,orThe complexity ofThe design. Constraining the components related toThe regional clock properly the tool toFind a solution. To debug your design withPartially routed results, please allowMap/placer toFinish the execution (by setting environmentvariableXil_par_debug_ioclkplacer to 1). Place:909-Regional Clock Net"i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>"Cannot possibly be routed to Component "i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_ IOB/U_ODELAY_DM"(PlacedinchClock region"Clockregionp_x1y2"), since it isToo far away from source BUFR"i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_ Bufr_rsync"(PlacedinchClock region"Clockregion_x1y4"). The situation is caused by user constraints,orThe complexity ofThe design. Constraining the components related toThe regional clock properly the tool toFind a solution. To debug your design withPartially routed results, please allowMap/placer toFinish the execution (by setting environmentvariableXil_par_debug_ioclkplacer to 1). Place:909-Regional Clock Net"i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>"Cannot possibly be routed to Component "i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[3].u_phy_dm_ IOB/U_ODELAY_DM"(PlacedinchClock region"Clockregionp_x1y2"), since it isToo far away from source BUFR"I_MIGDOUBLEINTERFACE/C1_U_MEMC_UI_TOP/U_MEM_INTFC/PHY_TOP0/U_PHY_READ/U_PHY_RDCLK_GEN/GEN_LOOP_COL1.U_BUFR _rsync"(PlacedinchClock region"Clockregion_x1y4"). The situation is caused by user constraints,orThe complexity ofThe design. Constraining the components related toThe regional clock properly the tool toFind a solution. To debug your design withPartially routed results, please allowMap/placer toFinish the execution (by setting environmentvariableXil_par_debug_ioclkplacer to 1). Place:909-Regional Clock Net"i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>"Cannot possibly be routed to Component "i_migdoubleinterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[1].u_phy_dm_ IOB/U_ODELAY_DM"(PlacedinchClock region"Clockregionp_x1y2"), since it isToo far away from source BUFR"I_MIGDOUBLEINTERFACE/C1_U_MEMC_UI_TOP/U_MEM_INTFC/PHY_TOP0/U_PHY_READ/U_PHY_RDCLK_GEN/GEN_LOOP_COL0.U_BUFR _rsync"(PlacedinchClock region"Clockregion_x0y4"). The situation is caused by user constraints,orThe complexity ofThe design. Constraining the components related toThe regional clock properly the tool toFind a solution. To debug your design withPartially routed results, please allowMap/placer toFinish the execution (by setting environmentvariableXil_par_debug_ioclkplacer to 1).

Personally think that there may be problems in the order, but the novice is not very familiar with the timing, do not know how to solve, found in the Xilinx website related issues after finding a solution.

Http://www.xilinx.com/support/answers/40977.html

At the end there is a description of MIG, following the above method, after regenerating the IP core, the problem is resolved. (Because the UCF file was changed directly before, there might be a problem here.) ）

About place:909 problem solving--DDR3 debug record