About the timer signal in the STM32 data sheet

First, we can see that this figure is about two points, one part is the clock source, the other part is the input and output

The clock source count, to the CNT counter, is then recorded or compared according to the capture comparison register. The records or comparisons have different configurations.

The first is TI signal
TI1 TI2 TI3 TI4: This signal is an external signal, is a direct connection with the pin signal, the diagram also has a problem is that the TI1 can be the first channel external signal to trigger,
can also be set to, first channel, second channel, third channel XOR or trigger. The external signal is sent to the filter and edge detector.

TIXFP trigger a valid signal.
TI1FP1 ti1fp2 ti2fp1 ti2fp2 ti3fp3 ti3fp4 ti4fp3 TI4FP4: This is a trigger effective signal, because the direct connection with the PIN can be set to the high and low edge trigger,
So by setting it up, TIXFP is the Peugeot that corresponds to whether the signal is valid.

ICX Map Signal
IC1 IC2 IC3 IC4: Channel effective signal, in front of him is the TIXFP and TRC signal, can be seen, TI1FP and TI2FP can correspond to each other IC1 and IC2,TI3FP and TI4FP can correspond to each other IC3 and IC4,
In this case, you can make a TIXFP signal corresponding to two icx, which corresponds to two channels.
In this way, the PWM input can be implemented, one to calculate the period and the other to calculate the duty cycle. The ICX signal is fed into the Prescaler

Channel interrupts and DMA output signals
The cc1i cc2i cc3i cc4i:icx signal passes through the Prescaler and can be configured to produce interrupts or DMA outputs.

Prescaler Count Signal
The ic1ps ic2ps ic3ps ic4ps::icx signal passes through the Prescaler to enter the CCRX count register, which can be read with the interrupt to CCR.

Oc1ref Output Valid signal
Oc1ref oc2ref oc3ref oc4ref: The first output signal when comparing the output or PWM output.
This signal is configured to high and low levels to become the output to the pin of the effective level.

Compare output PWM output level
OC1 oc1n OC2 oc2n OC3 oc3n OC4: signal output to pin

Brake Input PIN Signal
BRK brake input pin signal, pin input after entering polarity selection.

Brake Signal
BI: Brake signal, through the polarity of the selected signal and clock failure signal phase or after the effective braking signal. To drive the brakes.

Update Time
U update event signal, generated by software event Register or counter overflow.

Event Update interrupted
UI: Event Update interrupt Signal


External ETR trigger PIN signal
ETR: Special trigger PIN for trigger timer connected to external pin

ETR signal after Edge Prescaler
ETRP: ETR signal after Edge Prescaler

ETR effective signal after filtering
ETRF:ETRP after filtering, polarity, after the edge of the effective signal

Internal trigger ITRX channel signal
ITR0 ITR1 ITR2 ITR3: Trigger can be generated by the internal other timers, and timer 1 and Timer 8 timer trigger is different. In the data sheet of the timer chapter 74 is reflected

ITR Trigger Signal
The Itrx is set to generate a trigger signal. Go to the next step.

Edge Detector for TI1
The Ti1f_ed:ti1 edge detection signal, in Hall sensor mode, detects TI1 changes from the input to the ti1f_ed.
Whenever one of the 3 inputs changes, the counter is counted from the beginning of 0. This results in a time base triggered by any change in the hall input.

TRC: The trigger signal that is emitted after the TI1 edge and internal triggering is selected through the selector.

Trgi: The final trigger input.

TGI: Trigger input interrupt bit

Trgo: Trigger output. A trigger signal that controls other timers as the main mode should be connected to the Itrx of the other timers.

About the timer signal in the STM32 data sheet