Addressing of the Capability Structure in PCIe

PCI-X and PCIe bus specifications require that their devices must support the capabilities structure. The basic configuration space of the PCI bus contains a capabilities pointer register, which stores the head pointer of the capabilities Structure linked list. A PCIe device may contain multiple capability structures. These registers form a linked list, as shown in.

Each capability structure has a unique ID number, and each capability register has a pointer pointing to the next capability structure to form a one-way linked list structure, the pointer to the last capability structure of this linked list is 0. The pointer address starting with the linked list is 1 byte at 0x34. The addressing process is as follows.

 

 

1. We look at address 34 h and see the address of the next capability register set (50 h ).

2. we jump to 50 h and see a capability ID of 05 h (MSI capability structure ). we look at the next capability pointer in 51 H to find which address to jump to next (78 H ).

3. we jump to 78 h and see a capability ID of 01 H (power management capability structure ). we look at the next capability pointer in 79 H to find which address to jump to the next (80 h ).

4. we jump to 80 h and see a capability ID of 10 h (PCI Express capability structure ). we see 00 h as the next capability pointer in 81 h signifying the end of the linked list.

 

 

Reference: http://www.alterawiki.com/wiki/PCI_Configuration_Space