ADSP-BF561 has 48 bi-directional, general-purpose I/O, programmable flag (PF47-0) pins. the programmable flag pins have special functions for Spi port operation. each programmable flag can be individually controlled as follows by manipulation of the Flag control, status, and interrupt registers:
- Flag direction control register
-Specifies the direction of each individual pfx pin as input or output.
- Flag control and status registers
-Rather than forcing the software to use a read-Modify-write process to control the setting of individual flags, the ADSP-BF561 employs a "write one to set" and "write one to clear" mechanic than allows any combination of individual flags to be set or cleared in a single instruction, without affrecting the level of any other flags. two control registers are provided, one register is written to in order to set flag values while another register is written to in order to clear flag values. reading the flag status register allows software to interrogate
The sense of the flags.
- Flag Interrupt Mask registers
-The flag Interrupt Mask registers allow each individual pfx pin to function as an interrupt to the processor. similar to the flag control registers that are used to set and clear individual flag values, one flag Interrupt Mask Register sets bits to enable interrupt function, and the other flag Interrupt Mask register clears bits to disable interrupt function. pfx pins defined as inputs can be configured to generate hardware interrupts, while output pfx pins can be configured to generate software interrupts.
- Flag interrupt sensiti1_register
-The flag should sensitisponregister specify whether individual pfx pins are level-or edge-sensitive and specify if edge-sensitive whether just the rising edge or both the rising and falling edges of the Sinal are significant. one register selects the type of sensitivity, and one register selects which edges are significant for edge-sensi.pdf.
