After WINCE6.0 + I. MX515 is suspended, the hard reset system has no sound problems. wince6.0i. mx515

After WINCE6.0 + I. MX515 is suspended, the hard reset system has no sound problems. wince6.0i. mx515

After WINCE6.0 + I. MX515 is suspended, the hard reset system has no sound problems.

 

After the device is suspended, it is hard reset to start and the system has no sound. After being confirmed by hardware engineers, the power supply to the VDDD and VDDA of the audio module SGTL5000 is disconnected, and the two pins are still low during the hard reset startup process. Let's take a look at the power supply of these two pins.

Figure 1

1V2_DIG2 and 1V65 are powered by PMIC (MC13892) VGEN1 and VDIG respectively.

Figure 2

The voltage range of the audio chip VDDD is 1.1 ~ 2.0 V, the VDDA voltage range is 1.62 ~ 3.6 V.

 

It has been confirmed that the PMIC initialization code in eboot has not been set. Next we will write the code according to the relevant section of PMIC, but first let's look at the instructions on PMIC data.

1. VGEN1 part

Output of general purpose 1 regulator.

Figure 3

Because the voltage range of the audio chip VDDD is 1.1 ~ 2.0 V, marked as 1V2_DIG2 when the hardware is set, so we select output 1.20 V here. This corresponds to the following register control.

 

Figure 4

 

VGEN10 and VGEN11 of register 30 need to be set, corresponding code

//     VGEN = 1V2_DIG2 = 1.2 (power audio)if(!OALPmicWriteMasked(MC13892_REG_SET0_ADDR,                           CSP_BITFMASK(MC13892_REG_SET0_VGEN1),                           CSP_BITFVAL(MC13892_REG_SET0_VGEN1, 0)))    {       OALMSG(OAL_ERROR, (_T("OALPmicInit: Unable to configure VGEN1\r\n")));       goto cleanUp;           }

 

Figure 5

 

The VGEN1EN bit of register 32 needs to be enabled. The corresponding code is as follows:

//VGEN1 enable        if (!OALPmicWriteMasked(MC13892_REG_MOD0_ADDR,                           CSP_BITFMASK(MC13892_REG_MODE0_VGEN1EN),                            CSP_BITFVAL(MC13892_REG_MODE0_VGEN1EN,ENABLE)))    {       OALMSG(OAL_ERROR, (_T("OALPmicInit: Unable to enableVGEN1\r\n")));       goto cleanUp;           }

2. VDIG

Output regulator Digital. Low voltagedigital (DPLL, GPS ).

Figure 6

The voltage range of the audio VDDA is 1.62 ~ 3.6 V: 1.8 V is selected in the audio driver. To ensure consistency, 1.8 V is also selected here.

 

Figure 7

The VDIG0 and VDIG1 of register 30 need to be set. The corresponding code is as follows.

//VDIG setting        if (!OALPmicWriteMasked(MC13892_REG_SET0_ADDR,                            CSP_BITFMASK(MC13892_REG_SET0_VDIG),                           CSP_BITFVAL(MC13892_REG_SET0_VDIG, 3)))///1.8V                           //CSP_BITFVAL(MC13892_REG_SET0_VDIG, 2)))///1.65v                           //CSP_BITFVAL(MC13892_REG_SET0_VDIG, 0)))///1.05V    {       OALMSG(OAL_ERROR, (_T("OALPmicInit: Unable to configureVDIG\r\n")));       goto cleanUp;           }

 

Figure 8

The VDIGEN of register 32 needs to be enabled. The corresponding code is as follows:

//VDIG enable         if (!OALPmicWriteMasked(MC13892_REG_MOD0_ADDR,                           CSP_BITFMASK(MC13892_REG_MODE0_VDIGEN),                           CSP_BITFVAL(MC13892_REG_MODE0_VDIGEN, ENABLE)))    {       OALMSG(OAL_ERROR, (_T("OALPmicInit: Unable to enableVDIGEN\r\n")));       goto cleanUp;           }

Solve this problem.

 

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