An understanding of the S3C2440 clock settings

First, the S3C2440 has three internal clocks. 

Fclk: clock speed-mainly used as the kernel clock of the chip

Hclk: Bus clock-mainly used as LCD, USB, DMA clock signal

Pclk: interface clock-mainly used as serial port, gpio, SPI, ADC and other interface clock signals

 

2440 select the clock source fin (external crystal oscillator or external clock source) by setting the pins om2 and om3. The clock source signal fin generates the fclk, hclk, and pclk clock signals internally through the 2440 chip, these three clock signals drive the entire chip like an artery.

These three clocks are generally proportional, usually set to, that is, if the frequency of flck is 400 MHz, according to settings, then hlck is 100 MHz, plck is 50 MHz.

 

After talking about the 2440 clock signal, the following describes how to set the corresponding registers to achieve the desired frequency.

2440 is integrated with two phase-locked loops (mpll & upll) to increase the frequency of the input fin = 12 MHz crystal oscillator. S3C2440 uses three frequency doubling factors: mdiv, pdiv, and sdiv. The frequency doubling factor can be set through the Register mpllcon & upllcon. The mpllcon register is used to set the processor.Kernel clock speed (fclk ),The relationship between input and output frequencies is

 

Fclk = mpll = (2 * m * fin)/(p * 2 ^ s), where M = (mdiv + 8), P = (pdiv + 2 ), S = sdiv.

For example, if we want to generate a m flck, and the crystal oscillator input is 12 m, the above formula can be used to calculate the mdiv, pdiv, and sdiv values, which are about, 2, and 1. Generally, there is a table in the manual. You can directly find the size of the three multiplier factors.

 

 

Upllcon registers are used to generate 48 MHz or 96 MHz and provideUSB clock (uclk ),The relationship between input and output frequencies is

Uclk = upll = (M * fin)/(p * 2 ^ s), where M = (mdiv + 8), P = (pdiv + 2), S = sdiv.

The size of the three multiplier factors can also be obtained through the table.

Note: To set mpllcon and upllcon, you must first set upllcon and then set mpllcon.

 

After the phase-locked loop register is set, we also need to set the clock division controller clkdivn. Previously we mentioned that the relationship between the three clock can be achieved by setting this register.

 

 

To set the clock in a program, follow these steps:

1. Set the upllcon register (if needed)

2. Set the mpllcon register

3. Set the clock division controller clkdivn

4. Set the clock control register clkcon (if needed). This register is used to turn on and off the peripheral clock to reduce the power consumption of the system.

 

 

 

An understanding of the S3C2440 clock settings

1)Relationship between flck, hclk, and pclk

S3C2440 has three clocksFlck, hclk, and pclk

In the manual, P7-8 says:

Fclk is used by ARM920T,Kernel clock, clock speed.

Hclk is used for AHB Bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB Host block.That is, the bus clock, including the USB clock.

Pclk is used for APB bus, which is used by the peripherals such as wdt, IIS, I2C, PWM timer, MMC interface, ADC, UART, gpio, RTC and SPI. That isIO Interface clock. For example, the serial port clock settings are from pclk;

So what is the relationship between these three clocks?

These three clocks are usually set to a, relationship, that is, if the clock speed flck is 400 MHz, then set it to, then the hlck is 100 MHz, and the Plck is 50 MHz.

Register clkdivn indicates and sets the relationship between the three clocks

If clkdivn is set to 0x5, the ratio is, provided that camdivn [9] is 0.

 

2) Relationship between input clock fin and clock speed fclk

The modern CPU basically uses much lower clock input than the clock speed, and uses the phase-locked loop in the CPU for frequency doubling. For S3C2440, there are two common input clock Fin: 12 MHz and 16.9344 MHz. How does the CPU multiply the fin to fclk?

S3C2440 uses the mdiv, pdiv, and sdiv multiplier to set fin to mpll, that is, fclk.

Mpll = (2 * m * fin)/(p * 2 ^ s) where M = (mdiv + 8), P = (pdiv + 2), S = sdiv

The register mpllcon is used to set the multiplier factor.

 

In theory, you can set this register to implement different frequencies. However, it is not easy to set an appropriate frequency due to various constraints, the Manual lists some frequently-used tables,

 

For example, assume that the input clock fin = 16.9344 M, mdiv = 110, pdiv = 3, sdiv = 1,

Using the formula above, fclk = 2*16.9344*(110 + 8)/(2 + 3) * 2) = 399.65

 

3) about USB clock

S3C2440 has two Phase-Locked Loops. One primary phase-locked loop mpll is provided to fclk, And the other upll is provided to the USB clock (48 MHz), just like mpll, upll is generated by setting the frequency division factor in the upllcon register. The formula is slightly different:

Upll = (M * fin)/(p * 2 ^ s) where M = (mdiv + 8), P = (pdiv + 2), S = sdiv, same, you can use the table to obtain a proper value.

Finally, it is worth mentioning that the third-bit divn_upll in clkdivn is used to set the relationship between the USB clock uclk and upll. If the upll is 48 MHz, it should be set to 0, indicates the relationship between. Otherwise, the relationship is.

 

4) Finally, the clock settings of the bcng2440 Development Board are provided.

Fin = 1, 16.9344

Mdiv: 110 hdiv: 3 sdiv: 1, ratio:

Clkdivn: 5

Therefore, fclk = 399.65 MHz hclk = 99.91 MHz pclk = 49.95 MHz