Analog camera decoding module latest test TVP5150 module FPGA+SDRAM+TVP5150+VGA realization pal AV input VGA video output

Analog camera decoding module latest test TVP5150 module FPGA+SDRAM+TVP5150+VGA realization pal AV input VGA video output

Test using the TV set-top box AV analog signal input, VGA display output test, the effect is as follows

The FPGA uses Verilog programming, and the top-level RTL view is as follows

Module ACTION_VIP (

Input CLK,
Inputreset_n,
inputbt656_clk_27m,
Input[7:0]bt656_data,

Output [12:0] sdram_addr,//
Output [1:0] Sdr_ba,
Output [0:0] Sdr_cas,
Output [0:0] Sdr_cke,
Output [0:0] Sdr_cs,
inout [15:0] Sdram_data,
Output [1:0] SDR_DQM,
Output [0:0] Sdr_ras,
Output [0:0]sdr_we,
Output [0:0]SDR_CLK,

OUTPUTVGA_CLK,
Outputvga_blank,
OUTPUTVGA_HS,
Outputvga_vs,
Output[15:0]vga_rgb,

OUTPUTI2C_CLK,
Inouti2c_data
Output [5:0]leds

);

Wire Clk_sys;
Wire Clk_sys_p90;
Wire Clk_pixel;
Wireclk_xscale;
wireclk_24m;
Reg Clk_pixel;

Pll_xscalepll_xscale_inst
Pll_27mpll_xscale_inst
(
. Inclk0 (bt656_clk_27m/*clk_0*/),
. C0 (/*clk_xscale*/clk_pixel),
. C1 (Clk_sys),
. C2 (Clk_sys_p90)
);

/*
Odd_div # (
. Div_num (5)
)
Odd_div_inst (
. CLK (Clk_sys),//input Clk_sig
. Rst_n (Reset_n),//input Rst_n_sig
. Clkout (clk_24m)//Output Clkout_sig
);

*/

Assign clk_o = clk;//clk_24m;//

Assign SDR_CLK = Clk_sys_p90;
Assign sdram_addr[12] = 1 ' b0;

Video_process Tv_box
(
. Reset_n (Reset_n),//input Reset_n_sig
. Clk_sys (Clk_sys),//input Clk_sys_sig
. CLK_SDR (CLK_SDR),//input Clk_sdr_sig
. Clk_pixel (Clk_pixel),//input Clk_pixel_sig
. bt656_clk_27m (bt656_clk_27m),//input Bt656_clk_27m_sig
. Bt656_data (Bt656_data),//input [7:0] Bt656_data_sig
. VGA_CLK (VGA_CLK),//Output Vga_clk_sig
. Vga_blank (Vga_blank),//Output Vga_blank_sig
. VGA_HS (VGA_HS),//Output Vga_hs_sig
. Vga_vs (Vga_vs),//Output Vga_vs_sig
. Vga_rgb (VGA_RGB),//Output [23:0] Vga_rgb_sig
. SDR_ADDR (SDRAM_ADDR),//Output [11:0] Sdr_addr_sig
. Sdr_ba (SDR_BA),//Output [1:0] Sdr_ba_sig
. Sdr_cas (Sdr_cas),//Output [0:0] Sdr_cas_sig
. Sdr_cke (Sdr_cke),//Output [0:0] Sdr_cke_sig
. Sdr_cs (Sdr_cs),//Output [0:0] Sdr_cs_sig
. SDR_DQ (Sdram_data),//InOut [15:0] Sdr_dq_sig
. SDR_DQM (SDR_DQM),//Output [1:0] Sdr_dqm_sig
. Sdr_ras (Sdr_ras),//Output [0:0] Sdr_ras_sig
. Sdr_we (sdr_we)//Output [0:0] Sdr_we_sig
,. SDR_CLK (SDR_CLK)//Output [0:0] Sdr_clk_sig
);

I2c_av_config I2c_av_config_inst (//host Side
. ICLK (CLK),
. Irst_n (Reset_n),
I²c Side
. I2C_SCLK (I2C_CLK),
. I2c_sdat (I2c_data)
);

Endmodule

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Analog camera decoding module latest test TVP5150 module FPGA+SDRAM+TVP5150+VGA realization pal AV input VGA video output