Android under debug sound card driver I2S audio communication

I. Overview of I2S
The I2S (Inter-ic sound) bus is a bus standard developed by Philips for audio data transmission between digital audio devices, a bus dedicated to the

Data transfer between the two. A digital audio interface consisting of 4 lines, commonly used in HIFI,STB portable devices. Tx and RX signal lines are used for audio transmission. While the bit clock and the left and right clock

(LRC) for synchronizing links. The I2S is flexible because both the controller and the decoder can control the bit clock and the left and right clocks. Due to the sampling rate and the main system clock, the bit clock

With. The LRCLK is the same as the sampling rate. A few devices support independent ADC and DAC LRCLK. This makes it possible to synchronize capture and playback at different sample rates.

Second, I2S bus introduction

The I2S has 3 main signal lines: serial clock , frame clock , serial data, respectively.

Serial clock: SCLK, also called bit clock (BCLK), which corresponds to each bit of digital audio data, BCLK has 1 pulses.

The frequency of the BCLK =2x the sampling frequency x sample number of bits.

Frame clock: Lrck, (also called WS), used to toggle the data of the left and right channels, Lrck frequency = sampling frequency. Lrck to "1" indicates the number of right channels being transmitted

The "0" indicates that the data being transmitted is the left channel. The Lrck can change on the rising or falling edge of the serial clock, and the LRCK signal does not

The need must be symmetrical. At the slave end, the Lrck changes along the rising edge of the clock signal. Lrck is always a clock cycle before the highest bit transmission

Changes, which allows the slave to synchronize with the transmitted serial data, and enables the receiving side to store the current command and the next command

Clear the space.

Serial data: SDATA, the audio data expressed in twos complement. In I2S format, no matter how many valid data, the highest bit of data is always transmitted first (in

Lrck the 2nd BCLK Pulse at the beginning of a frame), so the highest bit has a fixed position, while the lowest position is dependent on the data

The number of significant digits. The effective number of bits on the receiver and the sender can be different. You can discard a data frame if the receiving end can handle fewer significant digits than the sender

If the receiver can handle more significant digits than the sender, it can make up the remaining bits on its own (usually up to 0). This synchronization mechanism enables

The interconnection of digital audio devices is more convenient and does not result in data dislocation. In order to ensure the correct transmission of digital audio signals, the sending and receiving terminals should be

Use the same data format and length. Of course, the data length can be different for the I2S format.

Sometimes in order to better synchronize between the system, but also need to transmit a signal mclk, called the main clock, also known as the system clock (Sys clock), is the sampling frequency

Rate of 256 times times or 384 times times.

Third, I2S data format

Depending on the location of the sdata data relative to Lrck and BCLK, it is divided into left-aligned, right-aligned, and I2S formats (i.e., standard format), in which the MSB is always the first

The main device that provides BCLK and Lrck clocks.

1, in the left alignment mode, the MSB can be in the bclk of the first rising edge of the following LRCLK transition.

2. In right-justified mode, the LSB can transition before the last rising edge of the BCLK LRCLK.

3. In i2s mode, the MSB can transition from the second rising edge of the BCLK following the lrclk of a transition.

4, some sound cards also support the DSP format, the format is not part of the I2S category.

LRP = 0

LRP = 1

Iv. Clock Relationship

In the Android system, play the audio file format: sample_rate=44.1khz,sample_length=16,channel=2, then BCLK should be

2x44.1khzx16=32xsample_rate, and in fact our mclk=11.289mhz,bclk=mclk/4,ample_rate=lrck=bclk/64=44.1khz,

BCLK does not match the value of the theoretical calculation. However, if the receiver can handle less significant bits than the sender, you can discard the extra low data in the data frame, if the receiving end can be

More effective digits than the sender, you can make up the remaining bits by yourself. "

Android under debug sound card driver I2S audio communication