Application of Video Decoder SAA7111 in Image Acquisition

Application of Video Decoder SAA7111 in Image Acquisition

[Date: 2008-7-18]

Source: China Power Grid Author: Wang yanchao, Zhao jinxian

[Font: large, medium, and small]

　

0 Introduction SAA7111 is a programmable Video Processor produced by philips. The chip integrates A/D and decoding functions. The chip is equipped with A phase lock, automatic clamping, automatic gain control, Clock generation, Multi-standard decoding, and other circuits. In addition, SAA7111 can also control the brightness, contrast, and saturation. It supports both PAL and NTSC. SAA7111A contains I2C interfaces, so you can set the operation mode of SAA7111A through the I2C bus. The VREF, HREF, RESO, and LLC2 of the field synchronization signal of SAA7111A can be directly extracted from the pins, saving the Time Synchronization Circuit, its Reliability and convenience have also been greatly improved, so it can be widely used in many systems such as projectors, digital TVs, DVD recorders and game consoles. 1. Structure and Functions of SAA7111 The internal function Diagram 1 of SAA7111 is shown in. In the figure, after a video image signal input from a certain pin of the four analog inputs AI11, AI12, AI21, and AI22 of SAA7111 is simulated, one channel can be output to the AOUT end through a buffer for monitoring, after A/D converter, A digital color signal and Brightness Signal are generated. After the Brightness Signal Processing and the color signal processing are performed respectively, the result of the Brightness Signal processing will be sent to the color signal processor for Comprehensive processing, the Y and UV signals are formatted and output from VPO (16 bits). The other one enters the synchronization separator, and the corresponding line and field synchronization signals HS and VS are generated by the digital PLL, meanwhile, the PLL will drive the clock generator to generate the HS-locked clock signals LLC and LLC2. All functions of SAA7111 are completed under the control of I2C bus. Among them, SCL is a serial clock, and SDA is a serial data signal. 2 Application of SAA7111 in Image Acquisition Figure 2 shows the hardware schematic of an image acquisition and control system based on wireless digital home security. The system can be equipped with four common cameras. When one channel is connected, the video signal will enter the video decoder SAA7111 for A/D conversion to convert the simulation information to the standard YUV4: 2: 2. Digital Image Information for further processing by the system. Which channel of SAA7111 is selected and the chip initialization can be controlled by the core controller AT91RM9200 of the system. AT91RM9200 initializes the chip through the I2C bus. SAA7111 has 32 internal registers (Sub-address00H-1FH) which are initialized to configure. Among these registers, 00H is the chip version information register, and 02H-05H is the frontend configuration Status Register, which is used to set the working status of the chip frontend analog channel based on the type and format of the input analog video signal: 06H-0DH and 10H-12H are the configuration registers for decoding operation, which are used for synchronous signal control and output data control; 1AH-1CH is the read-only test information register; 1FH is the read-only decoding Status Register, it can be used to report various signal states during decoding. Other registers can be reserved for backup. The system default value can be used for brightness, color, Saturation Control, and noise and signal gain processing. The optimal configuration can be obtained through comparison during testing. The system selects the default value. The initialization of SAA7111 mainly configures analog input control and output control. Through settings, the SAA7111 can work on a full-TV signal input of a simulated PAL system and output a 16-bit YUV4: 2: 2 digital video signal, outputs both HS, HREF, VREF, and VS signals. The specific settings of the internal registers of SAA7111 are as follows: (1) analog input control 1 (02 H), 2 (03 H), 3 (04 H), 4 (05 H) The low three-digit register 02H is used to set the analog signal input mode for SAA7111. A total of eight input modes are available. These eight input methods are divided into two categories: the first type is the input of A video signal, the data obtained by the signal after A/D sampling is sent to the color and brightness signal processing circuit at the same time; the second type is to input two channels of video signal. The data sampled by A/D is sent to the color signal processing circuit, and the data sampled by A/D is sent to the brightness signal processing circuit. The remainder of the 02H registers, together with 03 H, 04 H, and 05H, can be used to control the gain, amplitude, and noise of the input signal (optional ). The format of the analog input control register 1 is shown in table 1. Among them, MODE2, MODE1, and MODE0 are set bits in the input format and can be controlled in eight input modes. The specific functions of these eight modes are shown in table 2. In this system, the input signal format is CVBS and the input channel is AI11. Therefore, you can select MODE0, as shown in figure 3. (2) output format/latency Control 0 (10 H) The maximum two values ofts1 and ofts0 in this register are the output format selection bits, which are used to determine the four output formats. The setting methods for the four output formats are listed in table 3. During power-on initialization, the Register should be set to 40 h, and its output mode is yuv4: 2: 2 (16 bits ). (3) Output Control 1 (11 h) When the third position of the Register is 1, the VPO output is valid; when the second position is 1, the HS and VS outputs are valid. 3 Application Circuit of SAA7111 Figure 4 shows a typical application circuit of SAA7111. Based on the above settings, this design selects ai11 as the video input interface from the four analog video inputs of SAA7111. The output end outputs a High Brightness Signal and a low color signal. At the video input end, a capacitor of 10 NF and a resistance of 75 Ω must be connected. The SAA7111 clock can be an external clock and an internal clock. The system uses an external clock input. The xtal pin and the xtal1 pin indirectly input a 24.576 MHz Z crystal oscillator, which can be used to generate the clock required by the system. This design is driven by an external clock to generate the Line Lock clock LLC (27 MHz), llc2 (13.5 MHz) and the clock reference signal CREF (13.5 MHz, with a certain latency relative to llc2 ). It should be noted that the generation of the clock will be affected by the chip selection signal ce, which is only valid when the CE is high, and the SAA7111 is reset when the power is low, this pin does not generate periodic signals. In order to reduce the power supply ripple, each power input end should be added with a filter capacitor of 100 NF. Because SAA7111 is an analog-to-digital converter, both analog power and digital power supply, and analog and digital power cannot be used for simple co-power. Generally, single points of inductance can be used for single point grounding. Because the frequency of the digital circuit is high, the sensitivity of the analog circuit is strong. The digital and analog parts cannot interact with the signal current, and the ground line theoretically provides the power circuit, so in order to avoid interference, the inductor should be used to prevent the interference signal from returning. 4 Conclusion As SAA7111 integrates many complex functions such as analog-to-digital conversion, automatic clamping, automatic gain control, Clock generation, and Multi-standard decoding into one chip, the structure of SAA7111 is simple and easy to debug, the reliability has also been greatly improved, providing great convenience for various application systems that require image collection.