Application of textio in Simulation Based on VHDL Learning

Textio serves as a bridge between the VHDL simulation and the disk file, and uses text files to expand the simulation function of VHDL. This article introduces the textio package, describes how to use textio with an example of a modifier, and finally uses Modelsim to simulate the design and analyze the simulation results. During simulation of the VHDL source program, it is difficult to verify the result because some input and output relations rely only on the Input Waveform or the signal input in testbench. For example, to design an 8-bit calculator, it is very troublesome to verify all input, because it is necessary to fully determine whether the output is correct. In addition, if you use VHDL to design a processor, you need to read instructions. In this case, it is necessary to use text files.
Textio provides interaction with disk files during VHDL simulation. When verifying the divider, all input can be saved in one text file, and the results calculated by other software can be saved in another file. During the VHDL simulation, you can directly read the input file as the design input parameter, and automatically compare the result with the saved file to provide certain information to determine whether the result is correct or not. When debugging a processor written in VHDL, commands including the command type, source address, and target address can be saved as text files and textio can be used to read these commands. At the same time, the results and intermediate variables are saved as text files to determine whether the results are correct and the cause is easy to find. Because textio's text input and output functions are very limited, some companies provide packages to expand its functions, such as the std_iopak package in the std_javasskit library. In this article, we will only briefly introduce and use the textio package.
1 textio Introduction
Textio is a package in the STD of the VHDL standard library ). This package defines three types: line, text, and side. In addition, there is a subtype width. In addition, procedure is defined in the package ).

1.1 Type Definition
(1) type line is access string
Defines a line variable as an access type. It indicates that the variable is a pointer to a string and is the basic unit of all operations in textio. When reading a file, you first read a row of data by line, and then read data of various data types through line operations. When writing a file, you first combine various data types into line, then write line into the file. In use, you must note that only variables can be the access type, while signals cannot be the access type. For example, we can define
Variable dline: line;
But cannot be defined
Signal dline: line;
(2) type text is file of string
Defines text as the ASCII file type. Objects defined as text files are variable-length ASCII files. For example, two standard text files are defined in textio.
File input: Text open read_mode is std_input;
File output: Text open write_mode is std_output;
After definition, you can access the corresponding STD _ input and std_output files through the file type variables input and output.
(3) type side is (right, left)
Defines the side type. A Data Type named side is defined. There are only two statuses, right and left, respectively, indicating to write data from the left or right to the row variable. This type is mainly used when the textio package is included.
(4) subtype width is natural
Defines the width as a child type of a natural number. A child type indicates that its value range is a subset of the parent type range.

1.2 Process Definition
Textio provides basic processes for accessing text files. Similar to C ++, VHDL provides the overload function, that is, different processes that complete similar functions can have the same process name, but their parameter list is different, or the parameter type is different or the number of parameters is different.
The basic processes provided by textio include:

Procedure Readline (file variable; row variable); used to read a row of data from a specified file to the row variable.
Procedure writeline (file variable; row variable); used to write data contained in the row variable to the specified file.
Procedure read (row variable; data type); used to read data of the corresponding data type from the row variable.
　　
Depending on the data type and number of parameters, there are multiple overload methods. textio provides the bit, bit_vector, Boolean, character, integer, real, string, and time data types for heavy loads. At the same time, it provides a boolean data type overload that indicates whether the return process is correctly executed. For example, the process of reading integers is
Procedure read (L: inout line; Value: Out integer; good: Out Boolean); where, good is used to return whether the process is correctly executed. If it is correctly executed, true is returned.
Procedure write (row variable; Data variable; write mode; Bit Width );
This process writes data to the row variable. The write mode indicates whether to write data to the left or right of the row variable, and its value can only be left or right. The bit width indicates the Bit Width occupied by Data Writing. For example:
Write (outline, outdata, left, 2 );
Indicates writing the variable outdata to the left of the line variable outline takes 2 bytes.

2. textio application instance
The following describes the use of textio using a simple 8-bit calculator. The input data is two 8-Bit Signed numbers, and the output is nine-Bit Signed numbers to prevent overflow. When writing the description file of the calculator, you must first expand the two numbers and then perform addition operations. When writing a test file, note that there is a time difference between the read data and the result. Therefore, you need to insert a wait time period between the read result and the calculated result. The textio package is as follows:

-- textio.vhdllibrary std; use std.standard.all;    -- needed for bootstrap modepackage TEXTIO is  -- Type Definitions for Text I/O  type LINE is access STRING;    -- a line is a pointer to a STRING value  type TEXT is file of STRING;    -- a file of variable-length ASCII records  type SIDE is (RIGHT, LEFT);    -- for justifying output data within fields  subtype WIDTH is NATURAL;    -- for specifying widths of output fields  -- Standard Text Files  file INPUT: TEXT open READ_MODE is "STD_INPUT";    file OUTPUT: TEXT open WRITE_MODE is "STD_OUTPUT";  -- Input Routines for Standard Types  procedure READLINE (file F: TEXT; L: inout LINE);  procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out BIT);  procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out BIT_VECTOR);  procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out CHARACTER);  procedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out INTEGER);  procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out REAL);  procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out STRING);  procedure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN);  procedure READ (L: inout LINE; VALUE: out TIME);  -- Output Routines for Standard Types  procedure WRITELINE (file F: TEXT; L: inout LINE);  procedure WRITE (L: inout LINE; VALUE: in BIT;            JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);  procedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR;            JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);  procedure WRITE (L: inout LINE; VALUE: in BOOLEAN;            JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);  procedure WRITE (L: inout LINE; VALUE: in CHARACTER;            JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);  procedure WRITE (L: inout LINE; VALUE: in INTEGER;            JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);  procedure WRITE (L: inout LINE; VALUE: in REAL;            JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0;            DIGITS: in NATURAL := 0);  procedure WRITE (L: inout LINE; VALUE: in STRING;            JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);  procedure WRITE (L: inout LINE; VALUE: in TIME;            JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0;            UNIT: in TIME := ns);  -- File Position Predicates  function ENDLINE (L: in LINE) return BOOLEAN;end TEXTIO;

 

 

The eight-bit full processors are as follows:

 

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity Add2In is    port( D1        : in std_logic_vector(7 downto 0);            D2        : in std_logic_vector(7 downto 0);            Q         : out std_logic_vector(8 downto 0);            Clk    : in std_logic    );end entity;architecture beha of Add2In isbegin     process(Clk)    begin        if Clk‘event and Clk = ‘1‘ then            Q <= (‘0‘ & D1) + D2;        end if;        end process;end beha;

 

 

Compile the test file.
In the test program, read a line of content in the input file, and then extract two value input calculators from the line. Extract A value from the predefined result file and compare the calculation result of the calculator with the value. If the two values are different, the warning information is output. You can also write the output to a text file, and then compare the similarities and differences between the two text files to find out where the error occurred. Note that the textio package is used. In addition, the port in the test file is empty, which is equivalent to an independent circuit board. The component contains the previously defined divider. The function of this independent circuit board is to test the designed divider. The assert asserted statement is used in the program. Note that when the expression or variable after the statement is true, subsequent output is not executed. If the expression or variable is false, subsequent output is executed. In the program, the Conv _ STD _ logic_vector () type conversion function is also used to convert an integer to an 8-bit standard type. In addition, the variable dlatch is defined in the program. The function of this variable is to delay the comparison between the calculation result and the predetermined result by a clock cycle, and compare the period with the predetermined result.

LIBRARY ieee;                                               USE ieee.std_logic_1164.all;                                USE ieee.std_logic_arith.all;USE ieee.std_logic_signed.all;USE std.textio.all;ENTITY Add2In_vhd_tst ISEND Add2In_vhd_tst;ARCHITECTURE Add2In_arch OF Add2In_vhd_tst IS                                                  SIGNAL Clk : STD_LOGIC := ‘0‘;SIGNAL D1 : STD_LOGIC_VECTOR(7 DOWNTO 0):=(others => ‘0‘);SIGNAL D2 : STD_LOGIC_VECTOR(7 DOWNTO 0):=(others => ‘0‘);SIGNAL Q : STD_LOGIC_VECTOR(8 DOWNTO 0);SIGNAL SResult    :    INTEGER;SIGNAL OutData :     INTEGER;SIGNAL Dlatch    :    boolean := false;COMPONENT Add2In    PORT (    Clk : IN STD_LOGIC;    D1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);    D2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);    Q : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)    );END COMPONENT;BEGIN    i1 : Add2In    PORT MAP (    Clk => Clk,    D1 => D1,    D2 => D2,    Q => Q    );    init : PROCESS(Clk) BEGIN                Clk <= not Clk after 10ns;END PROCESS init;                                           always : PROCESS     FILE InputD    :    text open read_mode is "TestData.dat";    FILE OutputD    :    text open write_mode is "OutData.txt";    VARIABLE Dline    :    LINE;    VARIABLE Rline    :    LINE;    VARIABLE    Data1    :    INTEGER;    VARIABLE Data2    :    INTEGER;    VARIABLE    OutData    :    INTEGER;BEGIN                                                             WAIT UNTIL Clk‘event and CLk = ‘1‘;        readline(InputD, Dline);        read(Dline, Data1);        read(Dline, Data2);                D1 <= conv_std_logic_vector(Data1, 8);        D2 <= conv_std_logic_vector(Data2, 8);        OutData <= conv_integer(Q);                writeline(OutputD, Rline);        write(Rline, OutData);END PROCESS always;                                          PROCESSFILE InputR    :    text open read_mode is "Result.dat";VARIABLE    Rline    :    LINE;VARIABLE    Result    :    INTEGER;BEGIN    WAIT UNTIL Clk‘event and Clk = ‘1‘;        Dlatch <= true;        if Dlatch then            readline(InputR, Rline);            read(Rline, Result);            SResult <= Result;                    if(SResult /= Q) then                assert false report "Two values are different"                    severity warning;            end if;        end if;END PROCESS;END Add2In_arch;

 

Textio makes a great leap in the simulation of VHDL. It plays a very important role in describing models such as processors and determining the responsiveness of the system to irregular input. This article illustrates the textio library and its simple application process through simple examples. In the context of the wide application of embedded systems, textio is more necessary.

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Application of textio in Simulation Based on VHDL Learning