ARM Cortex A's SDRAM (DDR)

Source: Internet
Author: User

The initialization of SDRAM is described below.

SDRAM is a synchronous dynamic random memory, need to be initialized to normal use, but unfortunately it is too cumbersome to initialize, and there are also a lot of things involved, then we can summarize the following summary of what it needs to initialize the steps:

In the case of Samsung's s5pv210 series Chip, it uses 4 256M DDR2 memory chips, all 16-bit, which can be used as 2 32-bit memory chips in parallel. The 1Gb (1G bit) DDR interior is configured as a 8bank dram.

Initialize DDR2 requires 27 steps, I use this board, DRAM0 connection 256mb,dram1 connection 256MB

The first is three lines of code.

Ldrr0, =0xf1e00000//I don't know, the data sheet doesn't have a detailed description of it, so we don't have to talk about it.

LDRR1, =0x0//Don't Care

StrR1, [R0, #0x0]

It was written by Samsung itself, and I keep it all here.

Next is the DRAM1 and DRAM0 (bit between the 0~15 bits) to set the drive strength of the IO port, which can be seen on page No. 200 of the s5pv210 data sheet (the DDR portion of the SRAM), set to 1010 ... namely 0xAAAA;

Then the next thing is to set the clock (two DDR to set), first set the Cke low (pull down), and then set the clock signal, and then pull up cke (s5pv210 data Sheet 586)

The DDR is a synchronous clock, its clock comes from the CPU, and there is a PLL inside to multiply the frequency for faster speeds.

After that is the set memory chip, logically two memory counts as a piece of 32 bits of RAM, so say chip = 1;

Finally set the command register, write this register is sent command, and then used to configure the DDR working parameters.

There are a lot of parameters need to understand and set, can follow the data sheet to understand it, there is no need to write.

ARM Cortex A's SDRAM (DDR)

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