Arm exception Handling Process

Arm program in normal execution, encountered some special situation, need to put down the work that is being done, to solve the exception, and then return to the original place to continue to work, such a mechanism called arm exception handling mechanism.

First of all, the program is in normal execution, after encountering an exception, you can not directly solve the exception, because at the moment the program's variables, stacks and so on need to save, because wait until the exception returned, you have to continue to the original purpose in the place before the interruption. When the program handles the exception, it needs to save the scene and record the current state.

How is arm going to record the current state? The following aspects are specific:
1. Save the CPSR to the Spsr_<mode> in the corresponding exception mode, and when arm is in the thumb state, set the T bit to arm state and prohibit the interrupt flag bit;

2. Save the PC to the lr_<mode> in the corresponding abnormal mode;

3. Set the status register CPSR to the corresponding anomaly mode, CPSR the last four bit is the abnormal mode selection;

4. Point the PC register to the entry that handles the exception handler, i.e. the PC points to the exception vector table corresponding to the address of the exception type.

(1), resetting (reset)
(2), undefined instruction (UNDEF) (3), software interrupt (SWI) (4), instruction prefetch termination (Abort) (5), data access Exception (Dataabort) (6), external interrupt request (IRQ) (7), fast interrupt request (FIQ)

The exception vector table is a jump statement, because it occupies only four bytes, so the exception handler cannot be stored in the exception vector table, you need to jump to other places to execute the exception handler.

Therefore, before exception handling, the first thing to do is to complete these operations, but these are hardware auto-complete, so we do not have to worry about, but after the end of the exception handler, the process of returning to the previous state needs to be set by us.

When an unexpected end returns:

Recovering CPSR from Spsr_<mode>, that is, the state of the CPU before the exception is resumed

The lr_<mode> recovery pc,pc points to the point where the program was interrupted, but different exceptions are returned, and the PC is calculated differently, as explained below.

These operations are performed in the arm state.

Well, the exception handling mechanism is temporarily completed.

Here are some details of the problem, the above mentioned in the abnormal return, the calculation of the PC is different, then we say what the specific difference:

First we need to know, to tell the process of completing the instructions, arm state, when the exception is generated when the kernel will lr_<mode>=pc-4, meaning that this step is to record the return of the exception to execute the address.

However, the value of,lr_<mode> is to be adjusted according to the type of exception, as follows:

MOV R0, #1 pc-8 is executing

MOV R1, #2 pc-4 decoding saved here to Lr_<mode>

ADD R0,R0,R1 pc Fetch finger

One instruction (arm state, one instruction four bytes) divided into three stages: Fetch, decode, execute, fetch address (PC) = Address +8 being executed

(1) Return from software interrupt Swi and undefined exception:

MOV R0, #1 pc-8

MOV R1, #2 pc-4

ADD R0,R0,R1 pc

These two exceptions are an exception to the execution of an SWI instruction or an undefined instruction, i.e. an exception occurred during the execution phase, so the LR holds the MOV r1, #2这条指令的地址 (the PC now points to the address of the exception vector table's 0x8 (exception handler entry),

So the exception returned after the execution of the instruction is from MOV r1, #2这里开始, so the value of lr_<mode> directly to the PC can be, namely:

　　　　MOVS pc,lr_<mode>　　　

(2) exception returned from Fiq, IRQ, and prefetch instructions:

These two exceptions must wait until the current instruction to execute the exception handler, so after executing the current instruction, the prefetch instruction PC and decoding instructions have been updated (+4), such as: Performing mov r0, #8这条指令时, interrupt signal came,

But wait until this instruction executes to execute exception handler, at this time the exception processing returns to from MOV r1, #2这条指令开始执行.

MOV r0, #1 pc-8 <-Abnormal signal arrival

MOV R1, #2 pc-4

ADD R0,R0,R1 pc

But after performing mov r0, #1后, the PC has been updated, pointing to the next instruction, as follows:

MOV R0, #1 pc-12

MOV R1, #2 pc-8

ADD R0,R0,R1 pc-4

MOV r1,r0 pc

If the exception returns, at this time pc-4 is the add r0,r0,r1 instruction, but the program should be from MOV r1, #2这条指令开始, so can not directly lr_<mode> to the PC, but will lr_<mode>-4 to the PC, namely:

　　　　SUBS PC,LR, #4　

(3) prefetch instruction exception

The exception occurred while fetching the instruction, but was not responding to the exception during the execution phase,lr_<mode> to MOV r1, #2 address

MOV r0, #1 pc-8 <-exception handling

MOV R1, #2 pc-4

ADD r0,r0,r1 pc <-Abnormal signal arrival

This exception may be the fetch instruction when the memory does not have access rights or is empty, so in the exception handler to modify the memory content, on return to perform MOV r0, #1, so the return PC should point to MOV r0, #1, that

　　SUBS PC,LR, #4

(4) Return from data access exception:

LDR R0,R3 pc-8 <-anomaly Signal arrives

MOV R1, #2 pc-4

ADD R0,R0,R1 pc

This exception is an exception that is caused by access to data errors when the LDR R0,r3 is executed, and the LDR R0,r3 is re-executed when returned.

LDR R0,R3 pc-12

MOV R1, #2 pc-8

ADD R0,R0,R1 pc-4

MOV r1,r0 pc

At this point the PC has been updated, to re-execute LDR R0,R3, point the PCL to lr_<mode>-8, i.e.:

　　　　SUBS pc, LR, #8

So, to summarize, the address that the exception handler returns should be determined by the type of exception

(1) Judge the abnormal procedure in the execution of the instruction or after the execution of the instruction, that is, the PC has not been updated;

(2) Whether or not to re-execute the instruction after the exception program has finished processing.

Arm exception Handling Process