The arm instruction set is relatively simple. This article describes the important and difficult-to-understand aspects of arm instruction sets.
I. The arm instruction set is 32-bit, The program starts from the arm instruction set, including all abnormal interruptions are automatically converted to the arm State, and all commands can be executed with conditions.
2. The arm instruction set is load/store-type.You can only use the load/store command to access the system memory, while other commands are completed based on the internal register operations of the processor, which is different from Intel assembly, it is hard for beginners to understand.
Iii. Instruction Suffix:
"S" is an optional suffix. If S is specified, the condition code in CPSR is updated based on the command execution result. Many beginners do not know how to update. If this command is executed, it will affect the condition code mark (n, Z, C, V) of the arm Program Status Register.
"! "Indicates that after the data operation is completed, the base address register will be updated without additional time consumption.
For example, LDR r0, [R1, #4], which is equivalent to R0 <-mem32 [R1 + 4]
R1 = R1 + 4;
"^" Ldmfd R13 !, (R0-R3, PC) ^ // "^" represents a special form of instruction. (CPSR is also restored when the PC is installed from the memory ).
Iv. #Add 0x or & to indicate hexadecimal: # 0xff, # & FF
# Add 0b to sign to indicate binary.
# Add 0d to the end of the number to indicate decimal.
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5. Immediate addressing
Each immediate number is obtained indirectly using an eight-bit constant loop with an even number shifted to the right.
It is hard for beginners to understand: A 32-bit instruction cannot be used to store the 32-bit immediate number. Therefore, we analyze the instruction encoding format, only 12 digits are allocated in the instruction code to store the immediate number. Four digits are used to save the Right Loop value and eight digits are used to save a constant, therefore, not every 32-bit immediate number is valid.
6. Register addressing
Add R3, R2, R1, LSR #2 // The content of register R1 shifts two places to the right, but note that the content of R1 remains unchanged after this command is executed.
7. Forward address change, automatic address change, and post-address change
1. Forward address: LDR r0, [R1, #4] // Add 4 to the content of the R1 register, and then perform the operation. After the operation is completed, the content of R1 remains unchanged.
2. Automatic address change "! ", Indicating automatic address change (refer to the above three ).
3. Post-modification address: LDR r0, [R1], #4 // perform the first operation and then R1 + 4-> R1. After the operation is complete, R1 = R1 + 4. No "! .
8. Stack addressing
Note: Stack operations always require automatic address change. Otherwise, the previously saved content will be overwritten.
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9. Multiplication instructions
1. The multiplication command does not support the second operand as the immediate number.
2. The result register cannot be the first source register at the same time.
32-bit: Mul Rd, RM, RS
Mul Rd, RM, RS // RD and RM cannot be the same register
64-bit: Mul rdhi, rdlo, RM, RS // rdhi, rdlo, and RM cannot be the same register, and rdhi and rdlo cannot be the same register.
10. Jump command
1. The hardware automatically saves the next instruction address to LR (R14) and does not need to write the instruction.
2. When the instruction jumps beyond the 32 MB address space, unexpected results will be generated. Arm's instruction set is relatively simple. There are certainly other things to be noted about. You are welcome to actively participate in the supplement.
