ARM GIC-400 Register

1. Introduction

The GIC-400 is used to control interrupts. The A20 chip on the CUBIEBOARD2 uses this controller.

The address of the CUBIEBOARD2 GIC controller is 0x01c80000---0x01c87fff, and the length equals the length of the GIC-400 register.

The specific content is shown below.

With 0x01c80000 as the starting address, the offset is given below:

0x0000-0x0FFF	Reserved not used, useless
0x1000-0x1FFF	Distributor Configurator is useful
0x2000-0x3FFF	CPU interfaces CPU interface is useful
0x4000-0x4FFF	Virtual interface control block, for the processor, which is performing the access Virtualization-related, useless
0x5000-0x5FFF	Virtual interface control block, for the processor selected by address bits [11:9] Virtualization-related, useless
	0x5000-0x51FF 0x5200-0x53FF ... 0x5E00-0x5FFF	Alias for Processor 0 Alias for Processor 1 ... Alias for Processor 7
0x6000-0x7FFF	Virtual CPU Interfaces Virtualization-related, useless

Commonly used is the second and third block in the diagram, 0X1000~0X3FFF this part of the configuration.

2.Distributor Configurator

Distributor the address of this register = the address of the GIC controller + 0x1000, do not forget the offset when used. And start from here, like a register.

Offset	Name	can read and write	After reset	Role
0x000	Gicd_ctlr	RW	0x00000000C	Distributor Control Register Write to 1 enable controller, required
0x004	Gicd_typer	Ro	CONFIGURATION-DEPENDENT[D]	Interrupt Controller Type Register Where you can see the total number of broken lines
0x008	Gicd_iidr	Ro	0x0200143B	Distributor Implementer identification Register, GICD_IIDR Save a few version information, useless
0x080-0x0BC	Gicd_igrouprn	RW	0x00000000	Interrupt Group Registers[e] A bitmap that controls whether interrupts belong to group A or group B
0x100	Gicd_isenablern	RW[F]	SGIs and PPIs: 0x0000FFFF [G]	Interrupt set-enable Registers A bitmap that enables each interrupt to be written to 1 enable. Useful
0x104-0x13C			SPIs:0x00000000
0x180	Gicd_icenablern	RW[F]	0x0000FFFF[G]	Interrupt clear-enable Registers Similar to the previous register, with the opposite effect, write 1 is forbidden.
0x184-0x1BC			0x00000000
0x200-0x23C	Gicd_ispendrn	RW	0x00000000	Interrupt set-pending Registers Pend Bitmap, write 1 to enter Pend state
0x280-0x2BC	Gicd_icpendrn	RW	0x00000000	Interrupt clear-pending Registers Ditto, write 1 effect opposite, block pend state
0x300-0x33C	Gicd_isactivern	RW	0x00000000	Interrupt set-active Registers Bitmap, write 1 to activate interrupt
0x380-0x3BC	Gicd_icactivern	RW	0x00000000	Interrupt clear-active Registers Write 1 anti-activation interrupt
0x400-0x5FC	Gicd_ipriorityrn	RW	0x00000000	Interrupt Priority Registers The priority of each interrupt is stored, and each 8 digits is counted as one
0x800-0x81C	Gicd_itargetsrn	RO[H]	-	Interrupt Processor Targets Registers[i] Which processor the interrupt should be destined for processing
0x820-0x9FC		RW	0x00000000
0xC00	Gicd_icfgrn	Ro	SGIs:0xAAAAAAAA	Interrupt Configuration Registers, GICD_ICFGRN Whether the configuration interrupt is a low-level trigger or a falling edge trigger
0xC04		Ro	PPIs:0x55540000
0xC08-0xC7C		RW[J]	SPIs:0x55555555
0xD00	Gicd_ppisr	Ro	0x00000000	Private peripheral Interrupt Status Register, GICD_PPISR Generally useless
0xD04-0xD3C	Gicd_spisrn	Ro	0x00000000	Shared Peripheral Interrupt Status Registers, GICD_SPISRN Useless
0xF00	Gicd_sgir	WO	-	Software Generated Interrupt Register Controlling soft interrupts
0xF10-0xF1C	Gicd_cpendsgirn	RW	0x00000000	SGI clear-pending Registers Pend bit of soft interrupt
0xF20-0xF2C	Gicd_spendsgirn	RW	0x00000000	SGI set-pending Registers Ditto, but write 1 o'clock stop pend
0xFD0	Gicd_pidr4	Ro	0x00000004	Peripheral ID 4 Register
0xFD4	Gicd_pidr5	Ro	0x00000000	Peripheral ID 5 Register
0xFD8	Gicd_pidr6	Ro	0x00000000	Peripheral ID 6 Register
0xFDC	Gicd_pidr7	Ro	0x00000000	Peripheral ID 7 Register
0xFE0	Gicd_pidr0	Ro	0x00000090	Peripheral ID 0 Register
0xFE4	Gicd_pidr1	Ro	0x000000B4	Peripheral ID 1 Register
0xFE8	Gicd_pidr2	Ro	0x0000002B	Peripheral ID 2 Register
0xFEC	Gicd_pidr3	Ro	0x00000000	Peripheral ID 3 Register
0xFF0	Gicd_cidr0	Ro	0x0000000D	Component ID 0 Register
0xFF4	Gicd_cidr1	Ro	0x000000F0	Component ID 1 Register
0xFF8	Gicd_cidr2	Ro	0x00000005	Component ID 2 Register
0xFFC	Gicd_cidr3	Ro	0x000000B1	Component ID 3 Register

3.cpu interface

The offset of the start address is

Offset	Name	Type	Reset	Description[a]
0x0000	Gicc_ctlr	RW	0x00000000	CPU Interface Control Register To enable the bit. Write to 1 Enable
0x0004	Gicc_pmr	RW	0x00000000	Interrupt Priority Mask Register Limit interrupts to the lowest priority, above this value cannot be interrupted, better write bigger
0x0008	Gicc_bpr	RW	0x00000002[b]	Binary Point Register The minimum value of the Binary point Register depends on which security-banked copy is considered: 0x2 Secure Copy 0x3 Non-secure Copy Priority grouping
0x000C	Gicc_iar	Ro	0x000003FF	Interrupt Acknowledge Register Read-only, interrupt ID
0x0010	Gicc_eoir	WO	-	End of Interrupt Register Write to tell the CPU that the interrupt has been processed
0x0014	Gicc_rpr	Ro	0x000000FF	Running Priority Register Current Interrupt Priority
0x0018	Gicc_hppir	Ro	0x000003FF	Highest priority Pending Interrupt Register [C] Highest priority interrupt number and its pend value
0x001C	Gicc_abpr	RW	0x00000003	aliased Binary Point Register[d] The minimum value of the aliased Binary point Register is 0x3 . Alias Register
0x0020	Gicc_aiar	Ro	0x000003FF	aliased Interrupt acknowledge Register[d] Alias Register
0x0024	Gicc_aeoir	WO	-	aliased End of Interrupt Register[d] Alias Register
0x0028	Gicc_ahppir	Ro	0x000003FF	aliased highest priority Pending Interrupt Register[c][d] Alias Register
0x00D0	Gicc_apr0	RW	0x00000000	Active Priority Register For saving and recovering
0x00E0	Gicc_nsapr0	RW	0x00000000	Non-secure Active Priority Register[d] For saving and recovering
0x00FC	Gicc_iidr	Ro	0x0202143B	CPU Interface identification Register, GICC_IIDR Save the version information
0x1000	Gicc_dir	WO	-	Deactivate Interrupt Register

ARM GIC-400 Register