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When analyzing UART in arm-Linux S3C2440, it is necessary to first understand the hardware knowledge of the serial port in s3c2440a. That is, this article ----
Hardware:
The s3c2440a serial port provides three independent asynchronousserial I/O Ports ). Each serial port can send and receive data in the normal interrupt mode or DMA mode. When the system clock is used, the maximum rate is 115.2kbps. if the external clock (uextclk) is used, the UART speed can be faster. Each serial port contains two 64-byte FIFO caches for sending or transmitting data.
The s3c2440a serial port has the programmable baud rate, infrared (IR) transceiver data, 1 or 2-bit stop bit (STOP), 5/6/7/8-bit data width and parity function (parity checking ).
Each serial port consists of a baud rate generating unit, a sending unit, a receiving unit, and a control unit. As shown in, the clock of the Potter generation unit can be pclk, fclk/N, or uextclk (external input clock ). The sending and receiving units include a 64-byte Guest OS (first-in-first-out queue) and a data er. When sending data, the data is written into the FIFO, copied to the data er, and then sent to the Data. Finally, the data is sent by a data transmitter (txdn. Similarly, when receiving data, one-bit data is received by the data receiving pin (rxdn) and then copied to the FIFO cache.
Register:
There are three serial control registers: ucon0 ~ Ucon1 corresponds to each serial port and is used to set the UART working mode, baud rate, and interrupt type.
Status Register: utrstat0 ~ Utrstat2, used for receiving/sending status indication during serial port operation
FIFO control register: ufcon0 ~ Ufcon2 is used to set the FIFO.
FIFO Status Register: ufstat0 ~ Ufstat2, used to indicate the status in the FIFO Cache
For the use of the arm-Linux S3C2440 serial port, it is mainly for the operation of the above registers.
The next article will analyze the implementation of the arm-Linux S3C2440 serial port Driver Based on the source code (software)