ARM Processor Quick Context Switch

Overview:
FCSE (Fast context Switch Extension, quick contextual switching) is located between the CPU and the MMU, and if two processes use the same virtual address space, two processes use the same virtual address space for the CPU. The fast context switching mechanism transforms the virtual address of each process so that the part of the system that is not in addition to the CPU sees the virtual address transformed by the fast context switching mechanism. The fast context switching mechanism converts the virtual space of each process into different virtual spaces, so that there is no need to remap virtual addresses to physical addresses when switching between processes.
Fast Context switching (FCSE) avoids the heavy overhead of rebuilding the MMU, invalidating the cache and TLB, and rebuilding the cache and TLB content by modifying the virtual addresses of the different processes in the system, avoiding the remapping of virtual addresses to physical addresses that are caused by switching between processes. thereby improving the performance of the system.

FCSE principle:
In arm systems, 4GB of virtual space is partitioned into 128 process space blocks, each of which has a block size of 32MB. Each process space block can contain a process that can use the virtual address space 0x00000000~0x01ffffff, which is the virtual space of the process that the CPU sees. System 128 process space block is numbered 0~127, the process space block of number I is actually using the virtual address space of i*0x02000000 to i*0x02000000+ 0x01ffffff, This address space is the virtual address space that is used by the process in addition to the other parts of the CPU that are seen in the system.
The fast context switching mechanism transforms each virtual address emitted by the CPU according to the rules above and then sends it to other parts of the system, as shown in Figure 5-1.

The conversion algorithm for address VA to MVA is as follows:
if (va[31:25] = = 0b0000000) Then
MVA = VA | (PID <<25)
Else
MVA = VA

If VA[31:25] is not equal to 0, the description address VA is the virtual address used by this process to access data and instructions in other processes, at which point the PID of the access process cannot be 0. Conversely, if va[31:25] equals 0, the address VA to be accessed is within the process's own address space, so a process context switch is made to convert VA to MVA, where the PID of the above formula is the PID number of the process.

FCSE Programming Interface:
The ARM processor uses the C13 register of the CP15 coprocessor for FCSE functions, and the C13 register is described in section 4th, "CP15 Register Introduction". 1.2. When a process switch is made, the write cache is emptied first, the page table address of the new process is written to the CP15 C2 register, and the PID number of the new process is written to the maximum of 7 bits of the CP15 C13 register. If the processor does not support the FCSE feature, then the cache and tlbs are invalidated, and the system rebuilds the cache and the tlbs. Let's compare the difference between the XScale processor and the memory switching operation function in process switching in the ARMV6 processor: the memory switching operation function in the
XScale processor process switch is as follows:
. Align 5
ENTRY (cpu_xscale_ SWITCH_MM)
Clean_d_cache R1, R2; The data cache is invalid between R1-referred address to R2 address
MCR P15, 0, IP, C7, C5, 0; Invalidates the system all instructions cache
MCR P1 5, 0, IP, C7, C10, 4; empty write cache write buffer
MCR p15, 0, R0, C2, C0, 0; Load new page table address
MCR P15, 0, IP, C8, C7, 0; make system all data and refer to Make tlbs cache Invalid
cpwait_ret LR, IP; return
the memory switch operation function in the ARMV6 processor process switch is as follows:
ENTRY (cpu_v6_switch_mm)
mov r2, #0
LDR R1, [R1, #MM_CONTEXT_ID]; Gets the PID number of the new process, which is actually the MM_CONTEXT_T member structure in the new process's struct MM_STRUCT structure CONTEXT ID
MCR p15, 0, R 2, C7, C10, 4; empty write cache write buffer
MCR p15, 0, R0, C2, C0, 0; Load new page table address
MCR P15, 0, R1, C13, C0, 1; Set context pid number
mov pc, LR; returns
only ARMv6 versions of processors in ARM processors support FCSE functionality.