ARM processor registers, arm and thumb status, 7 operating modes

* * ARM processor register, arm and thumb status, 7 operating mode

Category: Embedded

There are 7 types of ARM processor operating modes:

USR mode
Normal user mode, program normal execution mode

Fiq mode (Fast Interrupt Request)
Handle fast interruptions, support high-speed data transfer or channel processing

IRQ Mode
Handling normal interrupts

Svc Mode (Supervisor)
Operating system protection mode, handling software interrupts SWI reset

ABT Abort (Abort mode) {data, instruction}
Handles memory failures, implements virtual memory and memory protection

UND undefined (Undefined)
Handles undefined instruction traps and supports hardware coprocessor software emulation

SYS system mode (basically =USR) (System)
Running privileged Operating system tasks

User mode and Privileged mode

6 Different processor modes other than user mode are called privileged mode

In privileged mode , the program can access all of the system resources , or switch to processor mode at will.

In privileged mode, in addition to system mode , the other 5 modes are called exception modes .

Most user programs run in user mode, at which point the application does not have access to some system resources protected by the operating system, and the application cannot switch directly to processor mode.

In user mode, when processor mode switching is required, the application can generate exception handling and switch processor mode in exception handling.

Working status of ARM processing

In the ARM processor, the kernel supports both the 32-bit ARM instruction and the 16-bit Thumb instruction.

For ARM directives, all instruction lengths are 32 bits, and the execution period is mostly single-cycle, and instructions are conditionally executed.

The THUMB command is characterized by the following:

1, instruction execution conditions are often not used back.

2, the source register and the target register are often the same.

3, the number of registers used is less.

4, the value of the constant is smaller.

5, the bucket mover (barrel shifter) in the kernel is often not used.

This means that a 16-bit Thumb instruction can generally accomplish the same task as the 32-bit ARM instruction.

The relationship between the arm instruction and the thumb directive:

Thumb instruction is a subset of ARM directives
Can call each other, as long as they follow a certain calling rule
The relationship between the time efficiency and space efficiency of the thumb instruction and the arm instruction is:
60%~70% with storage space of approximately arm code
Instruction number is about 30%~40% more than arm code
Arm code is about 40% faster than thumb code when memory is 32 bits
Thumb is about 40~50% faster than arm code when memory is 16 bits
With thumb code, the power consumption of the memory is reduced by about 30%

arm instructions and thumb instructions between Toggle (interworking ) of Basic Concepts and child function calls when switching

The processor mode can be switched via the software or by an external interrupt or exception handling process.

When an unexpected interrupt occurs on the application, the processor enters the appropriate exception mode. In each exception mode, there is a set of registers that are used by the appropriate exception handlers to ensure that the registers in the user mode are not destroyed when entering the exception mode.

The system pattern is not entered by exception, it has exactly the same register as the user mode. However, the system mode is privileged mode, can access all system resources, and can be switched directly to the processor mode. It is primarily intended for use by operating system tasks. Typically, the operating system's tasks require access to all system resources, while the task still uses the user-mode register group instead of using the appropriate register group in the exception mode, which guarantees that the task State will not be destroyed when an abnormal interrupt occurs.

The high performance characteristics of the low density and narrow memory of the thumb instruction make it very widely used in most C code-based systems sinks, but in some cases the system can only use ARM directives, such as:

1, if there is a higher speed requirement, the arm instruction will provide higher performance in wide memory.

2, some functions can only be implemented by ARM instructions, such as:

Access the CPSR register to enable/disable interrupt or change the processor operating mode;

Access coprocessor CP15;

Execute DSP arithmetic instruction not supported by C code;

Exception Interrupt (Exception) processing. after entering an abnormal interrupt, the kernel automatically switches to ARM state. that is, in the exception interrupt handler the population of some instructions is arm instruction, and then as needed, the program can switch to the THUMB working state, before the exception interrupt handler returns, the program is switching to arm working state.

Note: An exception occurs when the processor is in a thumb state (such as IRQ, FIQ, Undef, Abort, SWI, and so on), and automatically switches to the thumb state when the exception handling returns.

ARM processors are always executed from the arm working state. Therefore, if you want to run the thumb program in the debugger, you must add an ARM program header for the thumb program, and then switch to the thumb work state to invoke the Thumb program.

In a real system, the kernel state requires frequent switching (Interworkong) to meet the system performance requirements. The specific switchover is achieved by Branch Exchange, or BX instructions. The instruction format is:

Thumb working State BX Rn

ARM Working status BX Rn

Where RN can be any of the registers R0 ~ R15. The instruction can complete the absolute jump in the 4GB address space by copying the contents of the register RN to the program counter PC, and if the state bit of the operand register Bit0 = 0, it enters the ARM working state, and if Bit0 = 1, it enters the Thumb working state.

Arm Registers there are altogether 37 registers :

ARM Processor operating mode registers:

Non-grouping register R0~R7
In all operating modes, the ungrouped registers point to the same physical register, they are not used by the system for a special purpose, so when running mode conversion in interrupt or exception handling, the use of the same physical register for different processor operating modes can cause data corruption in the register, This should be noticed when designing a program.

Packet Register R8~r12
Each physical register accessed is related to the current operating mode of the processor
R8~r12: Each register corresponds to two different physical registers
When using Fiq mode, the Access register R8_fiq~r12_fiq
When using a mode other than Fiq mode, the Access register is R8_USR~R12_USR.

R13, R14: Each register corresponds to 6 different physical registers
One of these is that user mode is common to system mode, and the other 5 physical registers correspond to 5 different modes of operation
Use the following notation to differentiate between different physical registers:
R13_
R14_
Mode is one of the following: USR, Fiq, IRQ, Svc, Abt, und.

Stack pointer-r13/sp

The

R13 is commonly used as a stack pointer in arm directives, but this is a customary usage, and the user can use other registers as a stack pointer.
    sub    sp, SP, #4       ; reserved for PC
    stmfd    sp!, {R8-R9}

Because each operating mode of the processor has its own independent physical register R13, in the initialization section, the R13 in each mode is initialized, Thus, when the program runs into the exception mode, the registers that need to be protected can be placed in the stack pointed to by R13, and when the program returns from the exception mode, it resumes from the corresponding stack.

Sub-Program connection Register-R14/LR

R14 is also known as the subroutine Connection register or the connection register LR. When executing the BL subroutine call instruction, a backup of R15 (program counter PC) can be obtained from R14. In other cases, the R14 is used as the general register.

In each mode of operation, the R14 can be used to save the return address of the subroutine, when the subroutine is called with BL or BLX instruction, the current value of the PC is copied to R14, after the subroutine is executed, and the value of the R14 is copied back to the PC, the call of the subroutine is returned.

BL SUB1
......
SUB1:
......
MOV PC,LR/* Complete subroutine return equivalent to BX LR */

Program Counter-R15/PC

Although R15 can also be used as a general-purpose register, it is important to note that there are special restrictions that, if these restrictions are violated, the result of the instruction execution is unpredictable.

Program Status Register (CPSR/SPSR)
CPSR (current program status register)
SPSR (Backup program status register)

The current program status register CPSR is accessible in all processor modes.

CPSR: The Program State Register (current program status register), which is accessed in any processor mode. It contains the conditional flag bit, interrupt stop bit, current processor mode flag, and some other control and status bits.
The CPSR is used to store the condition code at user-level programming.

SPSR: program State Save register (saved programs status register), each processor mode has a status register SPSR,SPSR is used to save the state of CPSR, so that the exception returns after the return of the exception when the state of work. This register is used to hold the contents of the current program State register when a particular exception interrupt occurs. you can use SPSR to recover CPSRwhen an abnormal interrupt exits. Because user mode and system mode are not abnormal interrupt mode, he has no spsr. When a user accesses SPSR in user mode or system mode, unpredictable consequences will occur.

The CPSR format is shown below. SPSR and CPSR formats are the same

Condition code flags for program status registers

N, Z, C, v are the condition code flag bits. Their contents can be changed by the results of arithmetic or logical operations, and can determine whether an instruction is executed
In arm state, most of the instructions are conditionally executed.
In the thumb State, only branch instructions are conditionally executed.

the low 8 bits of the status register (I, F, T, and m[4:0]) are called control bits, which can be changed when an exception occurs. If the processor is running privileged mode, these bits can also be modified by the program.

Interrupt prohibit bit I, F:
I=1 disable IRQ interrupts;
F=1 prohibit Fiq interrupts.

t flag bit: This bit reflects the operating state of the processor
The ARM architecture v5 and above versions of the T-series processor, when this bit is 1 o'clock, the program runs in the thumb state, otherwise it runs in arm state.
ARM architecture v5 and above for non-T series processors, when this bit is 1 o'clock, the next instruction is executed to cause an undefined instruction exception, when the bit is 0 o'clock, the operation is in arm state.
run mode bit m[4:0] is the mode bit that determines the operating mode of the processor

Register organization in Thumb state

Register relationship in thumb and arm state

ARM processor registers, arm and thumb status, 7 operating modes