As, PS, and JTAG configuration modes for Altera FPGAs

FPGA devices are available in three configurations: Active configuration mode (as) and passive configuration mode (PS) and most commonly used (JTAG) configuration methods.

as mode (Active Serial Configuration mode): Each time the FPGA device is power-up, the FPGA device The boot configuration operation process, which controls the external memory and initialization process, from the configuration device EPCS actively emit the number of reads The EPCS data is read into the FPGA, and the FPGA programming configuration data is DATA0 The foot is fed into the FPGA, the configuration data is synchronized on the DCLK input, and 1 clock cycles transmit 1 bits of data.

　　PS mode (Passive Serial config mode): The configuration process is controlled by an external computer or controller. Through the configuration devices such as the Enhanced Configuration device (EPC16,EPC8,EPC4), the EPCS as the control device, the FPGA as the memory, the data is written to the FPGA, to achieve the FPGA programming. This mode can be implemented on-line FPGA programmable. When downloading the configuration for Cyclone II devices, such as EP2C8, in the JTAG download mode corresponds. Sof,as download method corresponds to. pof.

　　Jtag Mode: JTAG is directly burned into the FPGA, because it is SRAM, after the power to re-burn. As is stored in the FPGA 's configuration chip and is written to the FPGA each time it is power-up.

In general, there should be two download modes, as and JTAG on the Cyclone II Development Board.

　　As is the download. pof file to EPCS. And JTAG is downloading the. sof file into RAM in the FPGA. For the principle of jtag, you can refer to the "ARM Jtag Debugging Principle" written by Open-jtag development team. JTAG, BDM are similar, in fact, the simulation function embedded inside the chip, the relatively simple debugging tools can be developed, eliminating the high-priced emulator.

JTAG debugging uses the several feet of TCK, TMS, TDI, TDO, and TRST. Where TRST is used to reset the Tapcontroller, it is not required. The TAP controller can also be reset by the TMS pin.

Test Clock Input (TCK)
TCK provides a separate, basic clock signal for tap operations, and all of the tap's operations are driven by this clock signal. TCK is mandatory in the IEEE 1149.1 standard.

Test Mode Selection Input (TMS)
TMS signals are used to control the conversion of a TAP state machine. The TMS signal allows you to control the switching of taps between different states. The TMS signal is valid on the rising edge of TCK. TMS is mandatory in the IEEE 1149.1 standard.
Test Data Input (TDI)
TDI is the interface for data entry. All data that is to be entered into a particular register is entered serially via a single, single-input (TCK-driven) interface. TDI is mandatory in the IEEE 1149.1 standard.
Test Data Output (TDO)
TDO is the interface for data output. All data to be output from a particular register is a serial output (driven by TCK) via the TDO interface. TDO is mandatory in the IEEE 1149.1 standard.
Test Reset Input (TRST)
The TRST can be used to reset (initialize) the TAP Controller. However, this signal interface is optional in the IEEE 1149.1 Standard and is not mandatory. Because the TAP Controller can also be reset (initialized) via TMS.
When the FPGA is working properly, its configuration data is stored in SRAM and must be re-downloaded when power is added. In an experimental system, a computer or a controller is usually used for debugging, so PS can be used. In the practical system, in most cases the FPGA must be actively guided to configure the operation process, when the FPGA will actively from the peripheral dedicated storage chip to obtain configuration data, and this chip in the FPGA configuration information is designed by the ordinary programmer to the design of the. pof format files in.

　　Dedicated configuration device: EPC model of memory

Common Configuration devices: epc1,epc2,epc4,epc8,epc1441 (now seems to have been phased out) and so on, for Cyclone II series devices, ALTERA also provides configuration devices for the as mode, EPCS series. such as Epcs1,epcs4 The configuration device is also serial configured. Note that they only apply to the Cyclone series. In addition to the single BIT configuration such as AS and PS, some devices now support parallel configuration such as Pps,fps, which improves configuration speed. Of course, the plug-in circuit and PS have some differences. There are also processor configurations such as Jrunner and so on, at least 10 kinds. For example, Altera Company's configuration mainly has Passive Serial (PS), Active Serial (AS), Fast Passive Parallel (FPP), Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial Asynchronous (PSA), JTAG and other seven configuration methods, wherein Cyclone support configuration has ps,as,jtag three kinds.

　　in the configuration of FPGA chip, as mode can be used, if using EPCS chip, through a load line for burning, then the beginning of the "Nconfig, nstatus" should pull up, if you consider a variety of configuration mode, jumper designs can be used. Let the configuration mode in the jumper switch, the resistance of the pull-up resistor can be used 10K.

　　Recommendations in PS mode: If you use a cable to configure the FPGA chip on the board, and this FPGA chip has a configuration core On the board, you have to isolate the cable and the configuration chip signal. General debugging will not be the configuration of the chip welding, this time with a cable download program. Only after the debugging is completed, the program is burned in the configuration chip, and then the chip welding, or configuration chip is easy to remove the kind of welding, This makes it easy to debug with a problem.

Recommendations in the AS mode: use a board with the as download, the configuration chip has been welded on the board, the original as mode in the configuration chip with the cable to download, will automatically prohibit the configuration of the FPGA, and PS mode needs to be isolated on the circuit.

Typically, you configure EPC2 and flex10k with JTAG, and then EPC2 configure FLEX 10K in PS mode.

download cable, Altera download cable is divided into byteblaster and BYTEBLASTERMV, as well as Byteblaster II, now also launched based on Usb-blaster. Since BB is basically already very few people use, and Usb-blaster is now too expensive, bbii support multi-voltage power supply 5.5v,3.3v,2.5v,1.8v; bbii supports three download modes: As, the Altera as serial configuration chip (EPCS series) can be programmed; PS can be FPGA is configured, JTAG can be programmed for FPGA,CPLD, the Altera configuration chip (EPC series), while BBMV

　　usually in the FPGA test board, (such as the Cyclone series), in the As+jtag way, so that you can use the JTAG side Debug, and the final program has been debugged, then use as mode to burn the program into the configuration chip, and so One obvious advantage is that when the as mode is not available for download, the Quartus II comes with tools to generate the. Jic file can be used in JTAG mode to verify that the configuration chip is damaged, as described in the attachment (this is written by Chun Loong, from the jar, if there is a copyright issue, please forgive).

　　Altera FPGA can be configured by MCU, CPLD and so on, the main principle is to meet the timing in datasheet but I'm not going to say much here.

　　When configuring, the Quartus software operation section:

(1). Assignment-->device-->device&pin options--> Select configuration Scheme, configuration mode, Configuration device Note: In a machine that does not support remote and local updates, configuration mode is not selectable, and the configuration device generates POF files based on different configurations, if selected automatically, Select the smallest density device and fit the design;
(2). You can define the role of the two-port pin after configuration, in just Device&pin option-->dual-purpose pins-->, can continue when the configuration is completed when the I/O port is used;
(3). There are also a lot of hook options available under the General menu, which is generally not changed by default, see Altera configuration handbook,volume2,sectionii for specific usage.
(4) The scope of application of files with different suffix names:
. SOF (SRAM Object File) when directly using PS mode to use the configuration data in the FPGA, usbblaster,masterblaser,bbii,bbmv applicable, Quartus II will be automatically generated, all Other configuration files are generated by SOF.
The. POF (Programmer Object File) is also automatically generated by Quartus II, bbii applicable, as mode will configure the data down to the configuration chip.
The. RBF (Raw binary file) is used for microprocessor binaries. Useful in Ps,fpp,pps,ppa configuration.
The RPD (Raw programming Data file) contains the binary file of bit stream, which can be configured with as mode and generated only by the POF file.
. Hex (hexadecimal file) 16 binary files, a lot of MCU.
. TTF (Tabular Text File) applies to Fpp,pps,ppa, and bit-wide PS configuration.
. SBF (Serial Bit stream File) is configured with the PS mode for Flex 10k and Flex6000.
. Jam File is designed for program, verify, Blank-check.

As, PS, and JTAG configuration modes for Altera FPGAs