ASIC Design Using Quartus II Software

ArticleDirectory

• Design Process Overview
• RTL Encoding
• Hierarchical Design
• System Level Design
• Time Series Convergence and ECO support
• Script capability
• Support for EDA verification tools
• System verification

 

With the increasing market pressure on our products, the cost of ASIC templates and development is rising, and FPGA Performance and system-level features are constantly improved, more and more traditional ASIC Applications are implemented through Altera hardcopy ASIC and FPGA.

The Altera us II design software provides the best method for performance and efficiency, which is similar to the traditional ASIC design process. Its features help you easily implement the design of Altera FPGA and hardcopy ASIC. In addition, Quartus II software also provides some innovative technologies to accelerate System Design and give full play to the advantages of FPGA in system verification.

Based on cutting-edge technology, the latest FPGA of Altera has higher logic density and more complex system-level features. Altera's low-cost hardcopy ASIC series share the same FPGA features, with lower costs, better performance, and lower power consumption, meeting the needs of a large number of customized ASIC Applications.

From the very beginning, you can use the same Altera Quartus II software to design FPGA and hardcopy series ASIC, allowing you to control performance and power consumption.

Design Process Overview

Quartus II software supports the same basic design, register transfer level (RTL) synthesis, layout cabling, and verification processes used by ASIC designers. However, unlike the custom ASIC design, some physical structure design and test design steps are required (1 ).

Figure 1. UseQuartus IISoftware can reduce some traditional ASIC Design Steps

Due to the inherent design characteristics of the Altera device, scanning insertion and clock tree are not required in the FPGA design process.

Developing ASIC requires careful design and careful placement of I/O units to support the latest complex standards and achieve signal integrity on all pins. Designers can use the FPGA us ii fpga design software to logically allocate configurable I/O units. It uses a simple form interface to allocate editors or scripts. The Quartus II software can also perform quick checks to enable pin allocation to take effect, as well as pre-specified I/O standards for normal operation.

ASIC testing and errors cover an important part of ASIC development. Test the required design functions and ASIC design implementation, using the Boundary Scan insertion, built-in self-test (BIST), Feature Analysis, lddq, and automatic test mode generation (ATPG) technology. FPGA already contains the Boundary Scan logic. In the ASIC design process, the designer must insert the Boundary Scan logic and perform simulation at the top layer of the actual design logic. FPGA has undergone a large number of tests in the production process. In the FPGA design process, engineers can focus their attention on testing the design functions and timing requirements, you do not need to perform design tests on components such as cross string analysis.

The FPGA of Altera contains an advanced and Low-skew clock network for clock distribution in the device. FPGA designers cannot customize clock networks as freely as ASIC designers do. However, the pre-defined Clock Tree Structure in FPGA greatly simplifies the design process and meets most application requirements.

RTL Encoding

When switching from ASIC design to FPGA design, developers should perform careful synchronization design practices. For long-term reliable operation and design of different device speed levels and device structures, synchronous design practices are necessary. To support ASIC designers, Quartus II software has developed an integrated design rule check function to enhance synchronization design practices.

Hierarchical Design

To support ASIC designers, the module-based design method of logiclock is developed for Quartus II software. This method is similar to the module-based design process in the ASIC design process. Using the logiclock method, system designers can divide a design into several functional modules and assign them to different design teams for independent design, optimization, and implementation. These modules can then be input to the top-level system design, while the design Performance Indicators of each module remain unchanged. The optimized modules can keep their performance indicators unchanged and continue to be used in subsequent projects.

System Level Design

Quartus II software provides fast System Design and innovative hardware/software balanced analysis features. The design of the Altera FPGA system can now use a large number of mature IP cores. IP addresses include embedded processors, communication functions, optimized DSP processing functions, and interfaces and peripherals.

The system-level integration tool of Altera qsys, which is included in the Quartus II software, uses the IP core as a parameter to automatically add and connect to the entire system. A key feature of qsys is the ability to implement early design testing of hardware and software compatibility through test files and simulation models before any hardware prototype is established. Designers can use the quick system generation function of qsys, which function should be used in balanced analysis hardware, and which function should be used in embedded software.

Time Series Convergence and ECO support

Implementation of time series convergence is very important in any ASIC or FPGA design process. Quartus II software now has automated tools and "Power Tools" to provide designers with control like ASIC. Altera's Quartus II software includes a set of integrated physical optimization tools, such as automatic register replication and register re-timing, to adjust the design performance. Quartus II users can also manually copy registers to reduce fan-out branches on key paths in the design and allocate paths on key time series paths. The us II software Time Series Convergence plane editor can display the time series between any two nodes in the plane configuration, and can manually adjust the logical layout for the optimal time series.

In a typical project development cycle, the technical specifications of the programmable logic part may change after the project development starts or all system elements are integrated. These last-minute design changes are generally called engineering change orders (ECOS ). After the design is fully compiled (such as integrated and layout cabling), ECO only makes minor changes to the design function. ECO support is a common component of ASIC design processes. Quartus II uses the chip editor and step-by-step adaptation technology to implement eco support at the HDL and table level.

Script capability

The ASIC design process is usually driven by user scripts or setup files. FPGA designers can find the same functionality in the Quartus II software. The Quartus II software can now be run on the graphic user interface or command line interface. The Quartus II software uses a subset of the popular Synopsys Design constraints (SDC) Rules used by many ASIC development tools to input design constraints. The Quartus II software also contains new TCL-based applications.ProgramYou can use APIs to customize the script design process.

Support for EDA verification tools

The first time ASIC designers try FPGA design, they will find that many of their frequently used ASIC verification tools can also be used in the Quartus II design process. Quartus II software output network table, can be used in typical ASIC design process analysis software, for example, EDA static timing analysis, HDL simulation, board-level timing analysis, and signal integrity analysis software.

System verification

Real-time in-system verification is a required step. The inherent features of FPGA can be verified in the system, which is superior to ASIC Technology. In addition to fast FPGA design iterations and immediate in-system testing, FPGA design tools such as Altera Quartus II have the ability to seamlessly add embedded logic analyzer to the design. Quartus II software can also gradually send debugging signals to the pins without changing the HDL source file. In the lab, the chip editor function can be used to modify and test the design. Within a few minutes, you can view the detailed design planning structure and modify it gradually.

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