Assemble common commands

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Edit common commands in this section 　　 The MOV instruction is a dual-operand instruction, and the two operands cannot be fully operated for the memory operand: DST = src 1. 　　The destination number can be a universal register, a memory unit, and a segment register (but not a CS segment register). 2. The immediate number cannot be sent directly to segment Register 3. Data 4 is not allowed to be transmitted directly in two storage units. 　　It is not allowed to transmit information directly between two segment registers PUSH-in stack instruction and POP-out-stack instruction:  stack operation is a "last in, first out" way of data manipulation. 　　The operand of the push SRC//word into the stack is not allowed to be used immediately, except for the General Register, Segment Register (all), and memory. 　　In the stack, the high-level byte first into the stack, the low byte after the stack. 　　POP DST//word out-of-stack operations can be general-purpose registers, segment registers, and memory, except that the immediate and CS-segment registers are not allowed. 　　After the pop SS instruction is executed, the stack area's position in the store changes. 　　 The position of the top of the stack is changed after the pop SP command is executed. 　　XCHG (Exchang) Exchange instruction: Swap the two operands. XCHG OPR1,OPR2//byte/word Perform the operation: Tmp=opr1 opr1=opr2 opr2=tmp 1. There must be one operand in the Register 2. Cannot exchange data with segment Register 3. 　　 Data cannot be exchanged between memory and memory. 　　XLAT (TRANSLATE) Swap instruction: Convert one code to another code. 　　 XLAT (OPR optional)//byte operation: The al= (bx+al) command executes using only the first address of the table that is pre-deposited in BX, and when executed, the content in AL is the code to be converted. 　　The LEA (Load effective address) Valid addresses transfer register instruction LEA REG,SRC//instruction sends the valid address of the source operand SRC to the specified register. Action: REG = easrc Note: src can only be the memory operand of various addressing methods, REG can only be 16-bit register MOV bx,offset oper_one equivalent to LEA bx,oper_one mov sp,[bx]//Will BX indirect Addressing the contents of successive two storage units into the SP LEA SP,[BX]//The contents of BX as a memory valid address into the SP in the LDS (Load DS with pointer) pointer to the register and DS instruction LDS REG,SRC//often specifies the SI register. 　　 Action: reg= (SRC), ds= (src+2)//The contents of the first two storage cells indicated in SRC are fed into the registers specified in the instruction, and the last two storage units are fed into the DS segment registers. 　　 The Les (Load ES with pointer) pointer-to-send register and ES instruction LES reg,src//Often specify the DI register to perform the operation: reg= (SRC), es= (src+2)///LDS is roughly the same, and the difference is that ES is replaced by DS. 　　The lahf  (Load AH with flags) flag bit sends the AH instruction LAHF//The low 8-bit status flag (condition code) in the PSW register into the corresponding bit of AH, SF send D7 bit, ZF send D6 bit ... 　　 Action: Low byte of AH=PSW. 　　SAHF (Store AH into flags) AH send flag Register instruction SAHF//send the corresponding bit of AH register to the lower 8 bits of the PSW register corresponding bit, ah D7 bit send sf,d6 bit to ZF ... 　　 Action: The low byte of the PSW =ah. PUSHF (PUSH the Flags) flag PUSHF//The value of the flag register is pressed onto the top of the stack, and the stack pointer SP value minus 2 is performed: Sp=sp-1, (SP) =PSW high 8 bit, sp=sp-1, (SP) =PSW low 8-bit PO PF (pop the flags) flag out the stack instruction Popf//and PUSHF, in contrast, eject two bytes from the top of the stack to the PSW register, while the stack pointer value plus 2 performs the operation: PSW low 8 bits = (sp), SP=SP+1,PSW high 8 bits = (sp), sp=s 　　p+1 input and output instructions (in,out): Only use accumulator ax or AL with ports on external devices to transfer information. 　　In (input) input instruction: information from I/O through the accumulator to the CPU in Al,port//Direct byte input, port is the peripheral ports number (that is, the port address), can only take 00H ~ 0FFH A total of 256 port address. In Ax,port//Direct word input, AX store two consecutive ports address Port+1,port in AL,DX//indirect byte input, port address range can be set by DX to 0000H ~ 0FFFFH A total of 65,536 ports address in AX,DX//indirect word 　Input　Out output command: The information is transmitted from the CPU via the accumulator to the I/O out port,al//Direct byte output, and the PORT rules are the same as in instructions. Out Port,ax out dx,al///indirect byte output out Dx,ax MOV al,05h out 27h,al//Transfer byte 05H to address 27H port Add (add) Add instruction + DST,SRC/ /byte/word perform operation: DST=DST+SRC 1. 　　The two memory operands cannot be added directly by the Add command, i.e. DST and SRC must have a common register operand. 2. 　　Segment registers cannot be used as SRC and DST. 3. The impact flag bit auxiliary crray flag,carry flag,overflow flag,parity flag,sign flag and zero flag as follows: CF is set according to whether the most significant bit is in (borrowed) bit: C 　　F=1, no cf=0 when entering (borrowing) bit. 　　Of is set according to the symbol of the operand and its change: if the symbol of the two operand is the same, and the sign of the result is opposite to of=1, otherwise 0. 　　ZF is set according to the result: not equal to 0 o'clock zf=0, equals 0 o'clock Zf=1 SF is set according to the highest bit of the result: the highest bit is 0, then sf=0. AF is set when the D3 is added to the D4 (borrowing) bit when there is an input (borrowing) bit, af=1 when there is no input (borrowing) bit, af=0 PF is not odd when the number of results is 1, if the number of 1 is odd when pf=0, and even when the pf=1 ADC (ADd with Carry) carries a carry addition 　　 Instruction ADC dst,src//byte/word: DST=DST+SRC+CF//differs from add in that the value of the carry flag bit is also added. Inc (INCrement) plus 1 instruction INC OPR//byte/word to do the following: Opr=opr+1 1. The OPR can be a register and a memory operand, but it cannot be an immediate number and a segment register 2. 　　 Affects the flag bit OF,SF,ZF,PF and AF without affecting the CF. The sub (SUBtract) does not have a borrow with the subtraction instruction SUB dst,src//byte/word to perform the operation: DST=DST-SRC 1. 　DST and SRC addressing methods and rules are the same as Add.　2. Affects all flag bits. 　　 (see Add for the judging flag) 　　sbb  (SuBtract with borrow) with borrow subtraction instruction SBB dst,src//byte/word perform operation: dst= DST-SRC-CF DEC (decrement) minus 1 instructions 　　 DEC OPR//byte/word Perform operation: OPR = OPR-1//except CF flag bit, the remaining flag bits are affected. NEG (NEGate) The command NEG OPR perform the operation: OPR = 0-OPR//The operand is reversed by a bitwise negation and added 1.