Assembly chapter II--Basic knowledge carding and summary

In the first chapter, we introduce the basic knowledge of assembly language, in the second chapter we mainly introduce registers.

The main components of the CPU are registers, in the 8086CPU there are 14 registers, respectively: AX, BX, CX, DX, SI, DI, SP, BP, IP, CS, SS, DS, ES, PSW. All registers of 8086CPU are 16-bit and can hold two bytes. The 4 registers, AX, BX, CX, DX, are typically used to hold general data, called general-purpose registers. Since the registers in the previous generation of the 8086CPU CPU are 8-bit, for compatibility, the 4 registers of the 8086CPU ax, BX, CX, DX can be divided into two independent 8-bit registers:

? Ax can be divided into Ah and Al ? BX can be divided into BH and bl　　? CX can be divided into ch and cl　　? DX can be divided into DH and DL　

For compatibility issues, 8086CPU can handle data in two sizes:

Bytes: Byte, a byte consisting of 8 bits, can be stored in a 8-bit register

Word: recorded as word, consisting of two bytes, these two bytes are called High and low bytes, respectively.

To control the CPU by assembling instructions:

is not case-sensitive when writing a assembler instruction or a register name.

Changes to the data in the register after each instruction in the program segment of the CPU is executed:

The last instruction in the program section add AX,BX, the data in AX and BX before execution is 8226H, the added data is: 1044CH, but Ax is a 16-bit register, only 4 hexadecimal data can be stored, so the highest bit 1 cannot be saved in Ax, The data in AX is: 044CH, the highest bit of 1 is not out of the way, but there are other locations, along with our language in the slowly deepening, we will experience the programmer's cleverness and wit.

Note: Ax two separate registers AH and al, they are irrelevant, do not mistakenly think that Al's data added after the number of bits stored in AH!

Each memory cell has a unique address, called a physical address.

8086CPU of 16-bit structure:

1. The operator can process up to 16 bits of data at a time.

2. The maximum width of the register is 16 bits.

3. The path between the register and the operator is 16 bits.

8086CPU has a 20-bit address bus that can reach the 1MB addressing capability, how does it use 16-bit addresses to reach 20-bit physical addresses?

8086CPU uses the method of two 16-bit address synthesis internally to describe a 20-bit physical address.

Logical Structure:

Address adder using: Physical address = Segment Address *16+ offset address method to synthesize

"Physical Address = Segment Address *16+ offset address" essential meaning: When the CPU accesses memory, it adds a base address (segment address *16) and an offset address relative to the base address to give the physical address of the memory unit.

Paragraph concept: each segment has a segment address, but the memory is not divided into a paragraph, but because the CPU is divided.

Since the 16-bit address is 64KB, the maximum length of a segment is 64KB, and the starting address of the segment must be a multiple of 16, with a range of 0~FFFFH.

8086CPU has 4 segment registers: Cs,ds,ss,es.

CS and IP are the two most critical registers in 8086CPU, CS is the code segment register, and IP is the instruction pointer register.

How 8086CPU reads and does work:

CS and IP values can be modified: each time the IP is updated according to the space size of the instruction.

Simple modification of CS, IP instructions: JMP instructions.

① simultaneously modify CS, IP content: JMP segment Address: offset address

② only modifies the contents of the IP: a valid register in JMP

Assembly chapter II--Basic knowledge carding and summary