Assembly-Control transfer instruction JMP

Jump instructions are divided into three categories:
First, unconditional jump: JMP;
Second, according to the value of CX, ECX Register jump: JCXZ (CX is 0 jump), JECXZ (ECX for 0 jump);
Three, according to the EFLAGS register flag bit jump, this too many.

JMP Unconditional Transfer Instructions

1, the direct short transfer within the paragraph 2, a direct near-transfer within the paragraph 3, within the paragraph near the transfer of 4, the direct transfer between the section 5, the indirect far transfer between sections Conditional Transfer Directives

1) Transfer According to the setting of a single condition flag :

JZ (JE)   ; 0 (equals) jumps jump   if zero,jnz (JNE)  ; not 0 (equals) jumps

JS ; The result is negative to     transfersignJNS; The result is a regular transfer JO ; overflow then transfer overflow Jno ; Transfer without overflow　　 　　　　

JP(JPE)     ; the parity bit is 1 jump parity JNP (JPO)     ; the parity bit is 0 jumps JB (or Jnae, or JC)   , below, or no higher or equal, or carry is 1 transfer JNB (or Jae, or JNC)  ; no less than, or above or equal, or carry zero is transferred

2) compare two unsigned numbers and transfer according to the comparison results

JB (Jnae or JC) is actually jnae:jump not above and equal less than, that is, not higher and not equal, or a carry bit of 1 is transferred

JB   ; no sign is less than jump JNB  ; no symbol is less than the jump Jbe  ; no symbol is less than or equal to jump

Jnbe unsigned no less than equals jumps

But the execution of this statement  before JB used CMP to compare 2 unsigned numbers, CMP compared unsigned number after the effect is CF, so JB should be judged by CF

(Note: The comparison of unsigned numbers is here with above and below, with the comparison of signed numbers here with greater than less than)

Jump related flag bit:

One of AF PF

	Ten	9	8	7	6	5	4	3	2	1	0
	DF	IF	TF	SF	ZF						CF
Spill Out				Character No.	Zero	Not Use	Auxiliary Help	Not Use	Odd I	Not Use	Into -bit

D16 is the amount of displacement in its instruction call RET does not affect the condition code Interrupt instruction INT interrupts into overflow then interrupts Iret from interrupt return due to each interrupt vector occupying 4 bytes of unit. So the type number n specified in the interrupt instruction needs to be multiplied by 4 to get the interrupt vector of the type being developed.
Processor control and miscellaneous operation instructions

1, marking processing instructions

CLC ; cf=0 STC ; cf=1 CMC ; Cf=not CF CLD ; df=0 STD ; df=1 CLI ; if=0 (should be used with caution) STI ; if=1

2. Other processor control and miscellaneous operation instructions

NOP (no operation) No operation instructions The instruction does nothing, its machine code occupies a byte , which is often used in debugging programs to occupy a certain storage unit in order to replace it with other instructions when it is formally run. ( Role of occupying position, delay effect)

HLT (halt) shutdown instruction This instruction allows the machine to suspend operation, so that the processor is in a state of shutdown in order to wait for an external interrupt to arrive, after the interruption can continue to execute the following program.

Wait waits for the instruction to leave the processor in a idling state , which can also be used to wait for an external interrupt to occur, but still return the wait instruction after the interrupt has been completed.

ESC (Escape) swap instruction where mem points to a storage unit, the ESC command sends the contents of the storage unit to the data bus . Of course, the ESC directive does not allow immediate count and register addressing. This directive is using a coprocessor (coprocessor) when performing certain operations, it is possible to refer to an instruction or operand from memory. A coprocessor (e.g. 8087) is a hardware that can be matched to improve speed.

Lock block Directive The directive is a prefix that can be combined with other instructions to maintain the latch signal of the bus until the execution of its associated instruction is complete. This instruction avoids damaging useful information when the CPU is working in conjunction with other processors.

These instructions can control the processor state. None of this affects the condition code.

BOUND limit directive

ENTER IMM16,IMM8 to create a stack frame

LEAVE Releasing Stack frames

1. JMP (unconditional transfer instructions)

Execution code of the jump, divided into two, one: the transfer of the past code address and the current address in the same paragraph, as long as the IP (dedicated register-instruction pointer) can be modified; second: transfer between segments: that is, to jump past the code address and the current code address is not in the same paragraph, need to modify both CS and IP values

Writing:

1, JMP label; If the label is in the same code segment as the directive, the offset address of the Ip=label, otherwise Cs:ip=label's segmented address, simply, jumps to the label's address.

2, JMP reg16/mem16; transfer within paragraph, offset address =REG16/[MEM16]

3, JMP mem32; indirect transfer between segments, segment address Cs=mem32 high word, offset address ip=mem32 low word.

Note: When the operand is a memory operand, if the memory operand is a double-word type, the transfer between segments is generated, and if the memory operand is a word type, the indirect transfer occurs within the segment. When the type is not determined, the compiler will make an error .

32. JCC (conditional transfer Directive)

notation: JCC label;

Function: If the condition is true, then the offset address of the Ip=label, otherwise, the CPU will ignore the condition transfer, continue to execute the next instruction .

Conditional transfers are available in the following ways:

Table I: the JCC directive that tests a single flag bit:

JCC directive	Describe	Transfer conditions
Jc,jb,jnae	Transfer with rounding	Cf=1
Jnc,jnb,jae	No carry time transfer	Cf=0
Jz,je	is 0 (equal) when transferred	Zf=1
Jnz,jne	Non-0 (unequal) time transfer	Zf=0
Js	is a negative time shift	Sf=1
JNS	is a positive time shift	Sf=0
JO	Transfer when overflow	Of=1
JON	Transfer When not overflow	Of=0
Jp,jpe	The number of ' 1 ' is even when transferred	Pf=1
Jnp,jpo	The number of ' 1 ' is odd when transferred	Pf=0

Table II: JCC directives for the comparison of signed numbers (commonly used after CMP directives to determine the size of signed numbers)

Description

when less than or equal to (not greater than)

JCC directive	Transfer condition
Jg,jnle	greater than (not less than equals) when transferring	Sf=of and zf=0
Jge,jnl	is greater than or equal to (not less than) the transfer	sf=of
Jl,lnge	less than (not greater than or equal) when transferring	SF <>of
jle,lng	Transfer	Sf<>of or zf=1

Table Three:

Description

JCC directive	Transfer condition
Ja,jnbe	greater than (not less than equals) when transferring	Cf=0 and zf=0
Jae,jnb,jnc	is greater than or equal to (not less than) transfer	cf=0
JB,LNAE,JC	less than (not greater than or equal) when transferring	Cf=1
Jbe,lna	less than equals (not greater) when transferring	Zf=1 or cf=1

Assembly-Control transfer instruction JMP