Assembly Instruction Daquan

Source: Internet
Author: User
Tags integer division processing instruction

I.. data transmission Instructions

They transmit data between the memory and registers, registers, and input and output ports.
1. Generic data transfer instructions.
MOV transmits word or byte.
MOVSX the first symbol extension, then transfer.
MOVZX First Zero expansion, then transfer.
Push presses the word into the stack.
Pop the word pop-up stack.
Pusha the Ax,cx,dx,bx,sp,bp,si,di into the stack in turn.
POPA the Di,si,bp,sp,bx,dx,cx,ax to pop the stack in turn.
Pushad the Eax,ecx,edx,ebx,esp,ebp,esi,edi into the stack in turn.
Popad the Edi,esi,ebp,esp,ebx,edx,ecx,eax to pop the stack in turn.
Bswap switching the order of bytes in a 32-bit register
XCHG the interchange word or byte. (at least one operand is a register, and the segment register is not available as the operand)
CMPXCHG compare and swap operands. (The second operand must be an accumulator al/ax/eax)
XADD first exchange and then accumulate. (results in the first operand)
XLAT byte look-up table conversion.
──BX points to the starting point of a 256-byte table, and AL is the index value of the table (0-255, which is
0-FFH); Return to AL for table results. ([Bx+al]->al)
2. Input and output port transfer instructions.
In I/O port input. (Syntax: In accumulator, {port number │DX})
Out of the I/O port. (Syntax: Out {port number │DX}, accumulator)
When the input/output port is specified by an immediate method, its range is 0-255; When specified by the Register DX,
Its range is 0-65535.
3. Destination address delivery instructions.
The LEA loads a valid address.
Example: LEA dx,string; Save the offset address to DX.
LDS transmits the target pointer and loads the contents of the pointer into the DS.
Example: LDS si,string; save segment Address: Offset address to ds:si.
LES transmits the target pointer and loads the contents of the pointer into ES.
Example: LES di,string; save segment Address: Offset address to es:di.
The LFS transmits the target pointer and loads the pointer contents into FS.
Example: LFS di,string; add segment Address: Offset address to fs:di.
LGS transmits the target pointer and loads the contents of the pointer into the GS.
Example: LGS di,string; add segment Address: Offset address to gs:di.
LSS transmits the target pointer and loads the contents of the pointer into the SS.
Example: LSS di,string; save segment Address: Offset address to ss:di.
4. Flag delivery instructions.
LAHF Flag Register Transfer, mount the flag in AH.
The SAHF flags register is transmitted and the AH content is loaded into the flag register.
PUSHF flag into the stack.
Popf flag out of the stack.
PUSHD 32-bit flag into the stack.
POPD 32-bit flag out of the stack.

second, arithmetic operation instruction
Add addition.
The ADC carries a carry addition.
INC plus 1.
ASCII code adjustment for AAA addition.
The decimal adjustment of the DAA addition.
SUB subtraction.
SBB with borrow subtraction.
DEC minus 1.
NEC negation (minus 0).
CMP comparison. (two operands are subtracted, only the flag bit is modified, the result is not echoed).
The ASCII code adjustment of AAS subtraction.
The decimal adjustment of the DAS subtraction.
MUL unsigned multiplication.
Imul integer multiplication.
Above two, results echo Ah and Al (Byte operations), or DX and ax (word arithmetic),
The ASCII code of AAM multiplication is adjusted.
DIV unsigned division.
Idiv integer division.
Above two, result loopback:
Quotient Loopback al, remainder loopback ah, (byte operation);
or quotient loopback ax, remainder loopback DX, (Word arithmetic).
The ASCII code adjustment of the AAD division.
The CBW byte is converted to a word. (Extend the byte symbol in AL to AH)
The CWD word is converted to double word. (Extend the symbols in ax to the DX)
The Cwde word is converted to double word. (Extend the word symbol in AX to EAX)
CDQ double word extension. (Extend the symbols in the EAX to edx)

Three, the logic operation instruction
And and operations.
or OR operation.
XOR is different or operation.
Not negate.
Test. (two operand and operation, only change the flag bit, do not echo the result).
SHL logical left shift.
SAL arithmetic left shift. (=SHL)
The SHR logic shifts right.
SAR arithmetic right shift. (=SHR)
ROL the loop left shift.
ROR loop right.
RCL the loop left through the rounding.
The RCR is shifted right through the carry loop.
The above eight shift instructions, the number of shifts can be up to 255 times.
When a shift is made, the operation code can be used directly. such as SHL ax,1.
When the shift >1 times, the number of shifts is given by the Register CL.
such as MOV cl,04

Iv. sequence of instructions
Ds:si Source String Segment Register: source string variable address.
Es:di Target string Segment register: Destination string variable address.
CX Repeat Count counter.
Al/ax Scan value.
D flag 0 means that the SI and di should be automatically increment in the repetitive operation; 1 indicates that the amount should be automatically reduced.
The z flag is used to control the end of a scan or comparison operation.
MOVS string Transfer.
(MOVSB transmits characters.) MOVSW transfer Word. MOVSD transmits double word. )
CMPS string comparison.
(CMPSB compare characters.) CMPSW comparison word. )
SCAS string Scan.
Compare the content of the AL or ax with the target string, and the comparison results are reflected in the flag bit.
LODs loading a string.
Load elements (words or bytes) from the source string into either Al or Ax.
(LODSB transmits characters.) LODSW transfer Word. LODSD transmits double word. )
STOs Save the string.
is the inverse process of lods.
REP repeats when cx/ecx<>0.
REPE/REPZ when the zf=1 or comparison result is equal, and the cx/ecx<>0 is repeated.
REPNE/REPNZ when zf=0 or comparison results are not equal, and cx/ecx<>0 is repeated.
Repc when Cf=1 and cx/ecx<>0 are repeated.
REPNC when Cf=0 and cx/ecx<>0 are repeated.

v. Procedure transfer Instruction
1> Unconditional transfer instruction (long transfer)
JMP Unconditional Transfer Instructions
Call procedure Calls
The RET/RETF process returns.
2> Conditional transfer instruction (short transfer, 128 to +127 in distance)
(When and only if (SF XOR of) =1, OP1&LT;OP2)
Ja/jnbe is not less than or equal to the time of transfer.
JAE/JNB is greater than or equal to transfer.
Jb/jnae less than transfer.
Jbe/jna is less than or equal to transfer.
Above four, test the results of unsigned integer operations (flags C and Z).
Jg/jnle is greater than transfer.
JGE/JNL is greater than or equal to transfer.
Jl/jnge less than transfer.
Jle/jng is less than or equal to transfer.
Above four, test the results of signed integer operations (flags s,o and z).
JE/JZ equals transfer.
JNE/JNZ is not equal to the time shift.
JC is shifted when carrying a carry.
JNC is transferred without carrying.
Jno does not overflow when transferred.
Jnp/jpo parity is odd when transferred.
JNS is shifted when the sign bit is "0".
JO overflow transfer.
Jp/jpe parity is even when transferred.
The JS sign is shifted when the bit is "1".
3> Cyclic control instruction (short transfer)
Loop CX does not cycle at zero.
Loope/loopz CX is not zero and the flag is z=1 when looping.
LOOPNE/LOOPNZ CX is not zero and the flag is z=0 when looping.
JCXZ CX is shifted at zero.
The JECXZ ecx is shifted at zero.
4> Interrupt Instruction
INT Interrupt Instruction
Into overflow interrupt
IRET Interrupt Return
5> Processor Control Instructions
The HLT processor pauses until an interrupt or reset signal is present to continue.
Wait when the chip lead test is high and the CPU goes into a wait state.
ESC transitions to the outer processor.
Lock blocks the bus.
NOP empty operation.
STC place carry flag bit.
CLC clear carry flag bit.
The CMC carry flag is reversed.
STD set direction flag bit.
CLD clear direction flag bit.
STI place interrupt allow bit.
The CLI cleared interrupt allow bit.

VI. Pseudo-directive
DW definition Word (2 bytes).
PROC defines the process.
The ENDP process is complete.
SEGMENT defines a segment.
Assume establishes segment register addressing.
End of ENDS segment.
End program ends.

Seven, the Processor control command:
Flag processing instruction CLC (carry position 0 instruction)
CMC (Carry bit negation command)
STC (carry position is 1 instruction)
CLD (Direction flag 1 instructions)
STD (Direction flag position 1 instructions)
CLI (Interrupt flag 0 instruction)
STI (Interrupt flag 1 command)
NOP (No operation)
Wait (Waiting)
ESC (Exchange code)
Lock (Block)

Assembly Instruction Daquan

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