Assigning pins with TCL files

Prior to the simple design, the distribution of pins less, the Pin planner one input. Now in a large system, so it is too troublesome to search the Internet to use TCL files to allocate the Pin method.

The steps are as follows:

First generate TCL file, specifically project--generate TCL files for project, note Do not tick the include default assignments option, after the first tick, prompt error.

Then distribute the pins in the middle of the file in the following format.

Set_location_assignment pin_n8-to RESET

The resulting TCL file is as follows, #相当于注释的作用:

# Copyright (C)1991- -Altera corporation# Your Useof Altera Corporation's design tools, logic functions# andOther software andTools andIts AMPP partner logic # functions, andAnyOutputFiles from any of the foregoing # (including device programmingorSimulation files), andAny # associated documentationorinformation is expressly subject # to the terms andconditions of the Altera program License # Subscription agreement, Altera megacore Function License # Agreement, orOther applicable license agreement, including, # without limitation, that your UseIs forThe sole purpose of # Programming logic devices manufactured by Altera andsold by # AlteraorIts authorized distributors. Refer to the # Applicable agreement forfurther details.# Quartus ii:generate Tcl File forproject# file:daq.tcl# Generated on:fri Feb -  the: A: Wu  .# Load Quartus II Tcl Project packagepackage require:: Quartus::p rojectset need_to_close_project0Set Make_assignments1# Check the right project is openif{[Is_project_open]} {if{[stringCompare $quartus (Project)"DAQ"]} {puts"Project DAQ is not open"Set Make_assignments0    }} Else{# only Openif  notalready openif{[project_exists DAQ]} {project_open-revision Daq DAQ}Else{project_new-revision Daq DAQ} set Need_to_close_project1}# Make Assignmentsif{$make _assignments} {set_global_assignment-name FAMILY"Cyclone IV E"set_global_assignment-name DEVICE ep4ce10f17c8 set_global_assignment-name original_quartus_version13.0set_global_assignment-name project_creation_time_date"16:14:35 February"set_global_assignment-name last_quartus_version13.0set_global_assignment-name Project_output_directory output_files set_global_assignment-name min_core_junction_temp0set_global_assignment-name max_core_junction_temp -set_global_assignment-name Device_filter_package FBGA set_global_assignment-name Device_filter_pin_count theset_global_assignment-name Device_filter_speed_grade8set_global_assignment-name Error_check_frequency_divisor1set_global_assignment-name Eda_simulation_tool"Modelsim-altera (Verilog)"set_global_assignment-name Eda_output_data_format"VERILOG HDL"-section_id eda_simulation set_global_assignment-name Use_configuration_device OFF set_global_assignment-name Crc_error_open_drain OFF set_global_assignment-name Stratix_device_io_standard"3.3-v LVTTL"set_global_assignment-name cycloneii_reserve_nceo_after_configuration"Use as REGULAR IO"set_global_assignment-name reserve_data0_after_configuration"Use as REGULAR IO"set_global_assignment-name reserve_data1_after_configuration"Use as REGULAR IO"set_global_assignment-name reserve_flash_nce_after_configuration"Use as REGULAR IO"set_global_assignment-name reserve_dclk_after_configuration"Use as REGULAR IO"set_global_assignment-name Output_io_timing_near_end_vmeas"Half VCCIO"-Rise Set_global_assignment-name Output_io_timing_near_end_vmeas"Half VCCIO"-Fall Set_global_assignment-name Output_io_timing_far_end_vmeas"Half SIGNAL SWING"-Rise Set_global_assignment-name Output_io_timing_far_end_vmeas"Half SIGNAL SWING"-Fall Set_global_assignment-name Partition_netlist_type SOURCE-section_id Top set_global_assignment-name Partition_fitter_preservation_level placement_and_routing-section_id Top set_global_assignment-name Partition_color16764057-section_id Top set_global_assignment-name power_preset_cooling_solution"MM HEAT SINK with lfpm airflow"set_global_assignment-name Power_board_thermal_model"NONE (Conservative)"set_global_assignment-name Qsys_file qsys_files/Hardcore.qsys set_global_assignment-name Qip_file PLL.QIP set_global_assignment-name Bdf_file daq.bdf set_global_assignment-name Verilog_file ad_conv.v set_instance_assignment-name Partition_hierarchy root_partition-to | -section_id Top set_location_assignment pin_n8-To RESET set_location_assignment pin_e1-To sys_clk #SDRAM set_location_assignment pin_a14-To sdramclk set_location_assignment pin_d5-to dq[0] Set_location_assignment pin_b5-to dq[1] Set_location_assignment pin_d6-to dq[2] Set_location_assignment pin_c6-to dq[3] Set_location_assignment pin_b6-to dq[4] Set_location_assignment pin_b7-to dq[5] Set_location_assignment Pin_d8-to dq[6] Set_location_assignment Pin_c8-to dq[7] Set_location_assignment pin_a9-to dq[8] Set_location_assignment pin_a8-to dq[9] Set_location_assignment pin_a7-to dq[Ten] Set_location_assignment pin_a6-to dq[ One] Set_location_assignment pin_a5-to dq[ A] Set_location_assignment pin_a4-to dq[ -] Set_location_assignment pin_a3-to dq[ -] Set_location_assignment pin_a2-to dq[ the] Set_location_assignment pin_b11-to addr[0] Set_location_assignment pin_d12-to addr[1] Set_location_assignment pin_b12-to addr[2] Set_location_assignment pin_b13-to addr[3] Set_location_assignment PIN_C16-to addr[4] Set_location_assignment pin_b16-to addr[5] Set_location_assignment pin_c15-to addr[6] Set_location_assignment pin_a15-to addr[7] Set_location_assignment pin_b14-to addr[8] Set_location_assignment Pin_c14-to addr[9] Set_location_assignment pin_c11-to addr[Ten] Set_location_assignment pin_a13-to addr[ One] Set_location_assignment pin_a12-to addr[ A] Set_location_assignment PIN_B10-to ba[0] Set_location_assignment pin_d11-to ba[1] Set_location_assignment pin_b8-to dqm[0] Set_location_assignment pin_a10-to dqm[1] Set_location_assignment pin_a11-To CKE set_location_assignment pin_d9-To NCAs set_location_assignment pin_b9-To NCS set_location_assignment pin_c9-To NRAS set_location_assignment pin_e9-To nwe #FLASH set_location_assignment pin_h1-To dclk_epcs set_location_assignment pin_d2-To sce_epcs set_location_assignment pin_c1-To sdo_epcs set_location_assignment pin_h2-To Data0_epcs# Close Projectif{$need _to_close_project} {project_close}}

Then load the Tcl file, assign pins to the BDF file, and do the following:

TOOLS--TCL scripts, pop Up the dialog box, select the Tcl file to be loaded, click Run.

Assigning pins with TCL files