Asynchronous FIFO minimum depth calculation

Calculating the FIFO depth is a common problem in the design FIFO. Common sense tells us that when the read rate is slower than the write rate, the FIFO can be used as a buffer element or queue in the system. The size of the FIFO therefore basically implies the capacity of the required cache data, which depends on the rate at which the data is read and written. According to statistics, the system's data rate depends on the system's load capacity. So in order to ensure the FIFO size, we need to consider the worst case of FIFO transmission. The worst-case scenario is that the write rate is the largest and the read rate is the least, usually considering burst transmission.

First, asynchronous FIFO minimum depth calculation principle

If the data flow is continuous, the FIFO depth no matter how much, as long as the read-write clock is not homologous with the same frequency will be lost;
FIFO is used to buffer block data flow, generally used in write fast reading slow, followed by the following rules:

{FIFO depth/(write rate-readout rate)} = {FIFO is filled in time} > {packet delivery time}= {Write data volume/write rate}

That is, to ensure that there is no overflow on FIFO write data and no underflow when reading data from FIFO.

Example: A/D sampling rate 50MHZ,DSP read A/d read the rate of 40MHz, or the loss of 100,000 sampling data into the DSP, in A/d in and DSP at least a large capacity (depth) of the FIFO line?
100,000/50mhz = 1/500 s = 2ms
(50mhz-40mhz) * 1/500 = 20k is both FIFO depth.

A wrong algorithm (I also made the same mistake):
100,000/40mhz= 1/400s = 2.50ms
(50m-400m) *1/400 =25k. Then the data entered is not 100K, but 100k+50m* (0.0025-0.002) =125,000bit, error in the calculation of time.

Second, the asynchronous FIFO minimum depth commonly used calculation formula (if the read-write FIFO is simultaneous)

Write clock frequency W_CLK,
Read Clock frequency R_CLK,
Write clock cycle, each B clock cycle will have a data write FIFO
Read clock cycle, x data readout FIFO per y clock cycle
Then, what is the minimum depth of FIFO?

The calculation formula is as follows:

fifo_depth = burst_length-burst_length * X/y * R_CLK/W_CLK

This formula can be deduced from a principle.

Example Description:

If 100 write clock cycles can be written to 80 data, 10 read clocks can read 8 data. Make WCLK=RCLK, consider back-to-back (20 CLK non-data +80clk send data +80CLK data + 20 CLK non-outgoing data 200 CLK) into the formula to calculate the depth of the FIFO
Fifo_depth = 160-160x (80%) =160-128=32

If the Wclk=200mhz, instead of 100 wclk write 40, rclk=100mhz,10 RCLK read 8. Then the FIFO depth is 48
Calculated as follows Fifo_depth =80-80x (80%) X (100/200) =80-32=48

Note: fifo_depth = burst_length-burst_length * (x/y) * (R_CLK/W_CLK) is deformed to get fifo_depth = Burst_length-[(Burst_length * (1 /W_CLK)//(y* (1/R_CLK))/x] [(Burst_length * (1/W_CLK)]) indicates the duration of this burst, [(y* (1/R_CLK))/x] Indicates the time required to read each data (i.e., the actual speed of the read). The division of the two is naturally the amount of data read during this time. Obviously burst_length represents the amount of data written during this time, and the difference between the two is the residual data in the FIFO, which is the minimum depth of the theoretical FIFO. The actual application is usually half full signal to indicate the FIFO full state, so the actual design FIFO will leave at least one data space depth margin.

Third, the read-write FIFO is not simultaneous, the asynchronous FIFO minimum depth calculation

If the read/write FIFO is not simultaneous, this requires setting the FIFO depth to the maximum number of bursts of write data.

Fourth, asynchronous FIFO minimum Depth calculation example (1)

For setting a FIFO depth, this needs to refer to the specific application situation.

1. SDRAM application

such as: In the SDRAM application, the corresponding set a FIFO, the general setting depth of the operating data twice times enough, such as SDRAM full page read and write as 256, corresponding to the set depth of 512. Because the SDRAM read and write speed is definitely faster than the FIFO write speed, and the back of the FIFO read speed. As a result, the overall rate of operation is the same before and after SDRAM. There's nothing wrong with that.

2, two asynchronous clock data interface

Such as: Two asynchronous clock domain data interface, if read and write is carried out at the same time, usually set FIFO situation is the write clock is greater than the read clock. At this time, the depth of the FIFO is set to correspond to two clocks and the maximum burst data corresponding to write. Suppose the write clock frequency is 40MHz, the reading clock is 25Mhz, the maximum burst write data at the write end is 100 data. The corresponding setting depth calculation: 100 (1-25/40) = 37.5, the corresponding depth setting is at least 38. (Calculated in the formula 2nd)
If read and write is not simultaneous, this need to set depth to write data maximum burst number, as in the above example, the corresponding maximum burst number is 100, the depth is set to 100.

Fifth, asynchronous FIFO minimum depth calculation example (2)

1, a 8bit wide afifo, the input clock is 100MHz, the output clock is 95MHz, set a package is 4Kbit, and two package between the transmission space is large enough. To seek the depth of Afifo?

Formula: Fifo_depth = burst_length-burst_length * (x/y) * (R_CLK/W_CLK)

Burst_length = 4kbit/8bit, there are two kinds of results, one, according to the storage vendor's customary algorithm, 4kbit=4000bit,burst_length=500; Secondly, with the general binary algorithm, 4kbit=4*1024=4096bit, burst_length=512.

Because the values for x and Y are not given, the default is 1.

Available: First, fifo_depth = 500-500* (95/100) = 25, so the fifo_depth minimum value is 25.

Second, fifo_depth = 512-512* (95/100) = 25.6, so the fifo_depth minimum value is 26.

Disclaimer: Here reproduced elsewhere

Reference:

[1] http://blog.sina.com.cn/s/blog_6a89f7010100mnua.html

[2] Http://www.cnblogs.com/zhangzhi/archive/2009/11/04/1595808.html

[3] Http://www.cnblogs.com/yuphone/archive/2011/06/21/2085840.html

[4] Http://www.asic-world.com/tidbits/fifo_depth.html

[5] http://m282094986.blog.163.com/blog/static/38324693201301051444715/

[6] Http://bbs.eetop.cn/thread-383962-1-1.html

Asynchronous FIFO minimum depth calculation