Automatic build Makefile (1)--c/c++ compilation process &makefile rules Introduction

Objective:
You don't need to edit a slightly obscure makefile file when you build a C + + program using VS on Windows, and for starters, they don't even realize it's there. VS is to automatically generate makefile files and build the project. There is no denying that Visual Studio is an all-purpose IDE, it helps developers do a lot of work, but also reduce the threshold of the C + +, the significance is very significant.
But as an advanced C + + developer, you have to understand the underlying compilation and linking principles. Let's comb the process of compiling and linking the C + + code, and review makefile's writing rules, and finally let's try to implement the mechanism of automatically constructing the project makefile file. This article focuses on the compilation process and makefile rules of C + +, and then explains how to implement the makefile generator.

Compiling a C + + program
C + + program generation, divided into the following steps
1). preprocessing : Introducing the header file, parsing and expanding the macro definition
2). Compile : The simple point is to convert the source code into a sink code (machine instruction)
3). link : Assemble each sub-module and the corresponding library and generate the final executable program
　　
Commentary: Parameter-e is used to generate a pre-processed C + + file, the parameter-C is used to generate the compiled binary, the parameter-O is used to create a phase of the output name

Basic rules of Makefile
The basic rules are simple:

<target>: <prerequisites> <command>

Commentary: <target> is the target name, <prerequisites> is a dependent list item, <command> is the corresponding execution command
Of course there are some notes:
1). makefile The first execution rule is the default final target
2). The command must be "\ T" as the beginning
Makefile Common Macro Definitions:

$^ dependency list [email protected] target object $< the first object in a dependency list

The makefile variables are defined and used as follows:

CC = G++cflag =-g-wallapp:main.cpp $ (CC) $ (cflag)-o [email protected] $^

Commentary: variable cc/cflag shows the definition and reference syntax of makefile
　　Introduction of pseudo-target objects , especially useful for make clean

. Phony:clean Clean:-RM $ (OBJECTS)

In fact, the introduction of phony is for the file system, just known as "clean" file special case. Crossing, do you remember the summer rain at Daming Lake? That's the feeling.

Makefile's Little Combat
For the following projects:
　　
Include the project header file, SRC contains the project C + + file
Its specific makefile file can be edited as follows:

CC = G++cflag =-g-wallobjects: = $ (wildcard *.o) APP:APP.O cache.o g++ $ (cflag)-o [email protected] $^app.o:src/app . cpp include/cache.h g++-c-o [email protected] src/app.cpp-iincludecache.o:src/cache.cpp include/cache.h g++-c-o [Email protected] Src/cache.cpp-iinclude.phony:clean clean:-RM $ (OBJECTS)

Even if the project is complete, the makefile file has the functionality it needs: generate/Clear .

Challenge
Actual combat engineering or relatively small, manual maintenance makefile or relatively simple, if the project has hundreds of head file/C file it? Do you have a dependent library? Is it a problem?
If it is acceptable to write in increments, then a long, retrospective, or hand-over to others is a troublesome matter, isn't it?
Is it possible to automatically generate and maintain the makefile file, and what is its core idea? And how to do it? Please look forward to the following ...

Automatic build Makefile (1)--c/c++ compilation process &makefile rules Introduction