Automation variables in makefile $ @, $ %, $

In the automation variables $ @, $ %, $ in the makefile mode rule, the target and dependent file names of the Rule represent a class of file names; rule commands describe the reconstruction process of all such types of files. Obviously, no specific file names appear in the commands; otherwise, the pattern rules will become meaningless. How to represent files in the command line of the Pattern Rule will be the focus of this section. If you need to write a Pattern Rule to compile the. c file to the. o file, how do you write the correct source file name for gcc? Of course, you cannot use any specific file name, because the source file name varies with each execution mode rule. To solve this problem, you need to use "automatic environment variables". The values of automatic variables are determined based on the specific rules to be executed, depending on the target and dependent File Name of the rules to be executed. The following describes all the automation variables: www.2cto.com $ @ indicates the target file name of the rule. If the target file is a file (in Linux, The. a file is also called a static library file), it indicates the file name of the file. In a multi-target mode rule, it indicates the target file name of the trigger rule to be executed. $ % When the target file of the rule is a static library file, it represents a member name of the static library. For example, the target of a rule is "foo. a (bar. o) ", then the value of" $ % "is" bar. o ", the value of" $ @ "is" foo. a ". If the target file is not a static library file, its value is blank. $ <The first dependency File Name of the rule. If a target file is rebuilt using implicit rules, it represents the first dependent file added by implicit rules. $? List of all dependent Files updated with the target file, separated by spaces. If the object is a static library file name, it indicates the Library Member (. o file ). List of all dependent files under the www.2cto.com $ ^ rule, separated by spaces. If the target is a static library file, it represents only the names of all database members (. o files. A file can appear repeatedly in the target dependency. The variable "$ ^" only records its reference once. That is to say, the variable "$ ^" removes duplicate dependent files. $ + Is similar to "$ ^", but it retains the repeated files in the dependent files. It is mainly used for cross-reference of libraries when the program is linked. $ * Indicates "stem" in the mode rules and static mode rules ". "Stem" is the part represented by "%" in the target mode. (when a directory exists in the file name, "stem" also contains the directory (before the slash, see the matching section in 10.5.4 mode ). For example, the file "dir/. foo. b. When the target mode is ". %. B ", the value of" $ * "is" dir/. foo ". "Stem" is very useful for constructing related file names. Two notes are required for the automation variable "$ :? There is no "stem" for a clearly specified rule. In this case, the meaning of "$ *" changes. In this case, if the target file name has a recognizable suffix (refer to the 10.7 suffix rules section), "$ *" indicates the part of the file except the suffix. For example, for "foo. c", the value of "$ *" is "foo", because. c is a recognizable file suffix. GUN make's strange handling behavior for clear rules is to be compatible with other versions of make. In general, in addition to static rules and pattern rules, this variable should be avoided in rules that specify the target file.? This variable is blank when the target file name contains an unrecognized Suffix in the naming rule. Automated variable "$ ?" It is also very useful in explicit rules. You can use it to specify to operate only the dependent files after update. For example, the static library file "libN. a" consists of some. o files. This rule only adds the updated. o file to the Library: lib: foo. o bar. o lose. o win. o ar r lib $? In the automatic variable listed above. Four of them represent the file name ($ @, $ <, $ %, $ *) in the rule *). The other three represent a file name list in the rule. In GUN make, you can also use these seven automated variables to obtain the Directory and specific file names in a complete file name. Adding the "D" or "F" character to these variables forms a series of variant automatic ring variables. These variables will appear in previous versions of make. In the current version of make, you can use the "dir" or "notdir" function to implement the same function (refer to the 8.3 file name processing function section ). $ (@ D) indicates the directory part of the target file (excluding the slash ). If "$ @" is "dir/foo. o", the value of "$ (@ D)" is "dir ". If "$ @" does not contain a slash, its value is "." (current directory ). Note the difference between it and the function "dir! $ (@ F) the complete file name of the target file except the directory (actual file name ). If "$ @" is "dir/foo. o", "$ (@ F)" is only "foo. o ". "$ (@ F)" is equivalent to the function "$ (notdir $ @)". $ (* D) $ (* F) represents the Directory and file name in the target "stem" respectively. $ (% D) $ (% F) when the target static library is in the form of "archive (member, the directory and file name of the "member" member respectively. It is only valid for rule targets in this form. $ (<D) $ (<F) indicates the Directory and file name of the first dependent file in the rule. $ (^ D) $ (^ F) indicates the Directory and file of all dependent files (the same file does not exist ). $ (+ D) $ (+ F) indicates the Directory and file sections of all dependent files (repeated files may exist ). $ (? D) $ (? F) indicates the Directory and file name of the updated dependent files. When discussing automation variables, to distinguish them from common variables (such as "CFLAGS, we directly use the "$ <" format. This form is only used to distinguish it from common variables and has no other purpose. In fact, the name of the variable that represents the first dependent File Name of the rule is actually "<", we can use "$ (<) "To Replace" $ <". However, when referencing an automation variable, the common practice is "$ <", because the automation variable itself is a special character. GUN make also supports the "Sysv" feature and allows special variables to be referenced in the Rule dependency list (generally, automatic variables can only be referenced in the rule's command line) "$ @", "$ (@ D)", and "$ (@ F)" (Note: use "$ "), they represent "complete target file name", "directory part in the target file name", and "actual target file name part ". These three special variables can only be used in rules that specify the target file name or in static mode rules, and are not used in implicit rules. In addition, Sysv make and GNU make process different rule dependencies. Sysv make replaces and expands the rule dependencies twice, while GUN make only processes the dependency list once, and directly expands the variables and function references. This odd feature of automation variables is designed to be compatible with makefile files of the Sysv version. You can disable this feature when using GNU make, or use the pseudo target ". POSIX" in Makefile.