Aveon switching architecture port burst transmission

The aveon interface supports burst transmission. In burst mode, multiple transmissions are processed as one unit, rather than each data unit as an independent transmission. Burstable transmission maximizes the throughput of the slave port and achieves the highest efficiency when the slave port processes multiple data units from one master port.

Burst transmission ensures that the access to the target slave port from the master port during the burst transmission is not interrupted. Once the burstable transmission between a master-slave port pair ends until the burst transmission ends, the aveon switching architecture no longer allows any other master ports to access the slave port.
The main/Slave ports of aveon support burstcount transmission. The following describes the burstcount signal characteristics of the master-slave Port:
The burstcount signal width must be 2 ~ 32.
At the beginning of the burst transmission, the burstcount signal provides an encoded value indicating the number of consecutive transmissions contained in the current burst transmission.
The minimum value of burstcount is 1.
Burstcount with a value of 1 is equivalent to a single non-burst transmission.
When the burstcount width is N, the maximum burst length is 2n-1. At this time, the maximum burstcount is 1, and all other bits are 0.
The master port or slave port cannot be transmitted once per clock cycle during avron burst transmission. Burst transmission can ensure that the master-slave port is set for arbitration during the burst transmission period. The time required for burst transmission is uncertain, depending on the peripheral Logic of the master-slave port.
4.9.1 restrictions

Ports supporting burst transmission are subject to the following restrictions:
To support burstable read transmission on the primary port, the primary port must support pipeline transmission. Because the three-state attribute is not allowed for the main port in the pipeline mode, the three-state attribute cannot be used for the master port in the burst mode.
To support burstable read transmission from the port, the slave port must support:
A variable waiting period, that is, the port must contain waitrequest. Therefore, the creation and retention time cannot be used for the port. These two attributes are not allowed for the port with a variable wait period.
A variable latency pipeline transmission means that the port must contain the readdatavalid signal. Therefore, the slave port cannot use the three-state attribute, which is not allowed in the streamlined port with variable latency.
4.9.2 master port burst transmission

The burstcount signal is the output signal for the aveon main port. In addition to the burstcount signal, burst transmission also affects the signal behavior of address, read, readdata, eaddatavalid, write, writedata, and byteenable.
When the burst transmission starts, the master port issues a valid address on the address, and the burstcount sends the burst transmission length. The master port of each burst transmission sends only one address value. The aveon switching architecture automatically infers all the addresses transmitted during the burst transmission.
When the starting address of the master port is a and the burstcount value is B, the master port submits B continuous transmission starting from address. Burst transmission is not completed until data in Unit B is transmitted on the master port. Before the current burst transmission is completed, the master port cannot terminate the burst transmission or provide a new address.
4.9.2.1. Master port burst write Transmission

The start of Master port burst write transmission is similar to that of Master port basic write transmission. In addition to the burstcount signal, the main port sends the address, writedata, write, and byteenable signals (if needed. If the avron switching architecture is not ready, it sends a waitrequest before the rising edge of the next CLK. Finally, the aveon switching architecture invalidates waitrequest and captures the address and burstcount signals on the rising edge of the next CLK. The avron switching architecture also captures the first data unit of writedata on the rising edge of the CLK. The master port must remain unchanged during burst transmission.
The address and burstcount signals specify the remaining sudden transmission behavior. When a burstcount value greater than 1 is initiated on the master port, follow the following rules:
If the burstcount value of the master port is N, the master port must send a write signal on the rising edge of N clks to complete the burst transmission and provide new writedata. The arbitration of the arbitration port pair is locked until the master port completes the burst transmission.
The master port can delay the transmission by invalidating the write signal on the rising edge of the CLK, which prevents the aveon switching architecture from capturing the writedata of the current clock cycle.
The aveon switching architecture can delay transmission by sending waitrequest, which forces the master port to keep writedata and write unchanged within the clock period of an attachment.
The main port must be valid for all built-in byteenable signal lines during the entire burst transmission ..

Master port burst write Transmission

(A) The primary port sends out the first unit of address, burstcount, write, and writedata. In this example, the value of burstcount is 4.
(B) The availability of waitrequest IN THE aveon switching architecture indicates that it is not ready to handle burst transmission. As a response, the master port keeps all output unchanged.
(C) The waitrequest setting for the aveon switching architecture is invalid.
(D) capture the first unit (D0) of address, burstcount, write, and writedata on the rising edge of the CLK ).
(E) the addresses and burstcount of the master port are invalid. The two signals are ignored in the rest of the burst transmission. The main port provides the next unit (D1) of writedata ).
(F) aveon switching architecture captures the next unit (D1) of writedata on the rising edge of CLK ).
(G) The write setting on the master port is invalid, indicating that there is no valid writedata in this cycle.
(H) The write signal is invalid. Therefore, the avron switching architecture does not capture writedata on the rising edge of the data volume.
(I) The master port provides valid writedata (D2), and the write is enabled again.
(J) Capture writedata (D2) on the rising edge of the clk in the aveon switching architecture ).
(K) The primary port provides the last unit (D3) of writedata ).
(L) The aveon switching architecture sets waitrequest to be valid, causing the master port to remain unchanged throughout the clock cycle.
(M) The aveon switching architecture invalidates waitrequest.
(N) The aveon switching architecture captures the final unit (D3) of writedata on the rising edge of the CLK ). The master port burstable write transmission ends.
4.9.2.2 master port burst read Transmission
The burstable read transmission on the master port is similar to the delayed read transmission on the master port. The master port burstable read transmission has an obvious address and data phase, and uses the readdatavalid signal to indicate when the master port must capture readdata. The difference is that a single burst transmission address corresponds to multiple data stages.
The beginning of the master port burst read transmission is similar to the pipeline read transmission of the master port. In addition to the burstcount signal, the main port also sends the address and read signals. If the avron switching architecture is not ready, it sends a waitrequest signal before the rising edge of the next CLK. Finally, the aveon switching architecture invalidates waitrequest and captures address and burstcount on the rising edge of the next CLK. The address stage ends. Multiple Data stages start.
When the master port starts reading data with a burstcount value greater than 1, follow the following rules:
If the value of burstcount is set to N on the master port, the aveon switching architecture must ensure that the readdatavalid is issued on the rising edge of N clks to complete the burst transmission. The arbitration of the master port pair remains locked until the avron switching architecture returns all data for burst transmission.
The master port must capture readdata as long as the active signal of readdatavalid is set in the avron switching architecture. Each value of readdata is valid only in this clock cycle.
The main port must be valid for all byteenable signal lines during the entire burst transmission.

Master port burst read Transmission

(a) the master port issues address, burstcount, and read. In this example, the value of burstcount is 4.
(B) If the waitrequest parameter is set to valid in the aveon switching architecture, it indicates that it is not ready to handle burst transmission. As a response, the master port keeps all output unchanged.
(c) The waitrequest setting for the aveon switching architecture is invalid.
(d) Capture address and burstcount on the rising edge of the CLK. The master port can start a new transmission or burst transmission on the rising edge of the CLK. (This is not the case in this example).
(e) This is the oldest clock rising edge that avron switching architecture can return valid readdata. In this example, no readdatavalid is issued for the aveon switching architecture, so the primary port does not capture readdata.
(f) after a period of time, the aveon switching architecture provides valid readdata, and the combination of readdatavalid is valid.
(g) The first unit (D0) of readdata is captured on the rising edge of the CLK ).
(h) the main port captures the next unit (D1) of readdata on the rising edge of the CLK ).
(I) The aveon exchange architecture does not have valid readdata, so it sets readdatavalid to invalid. The aveon switching architecture can keep the eaddatavalid invalid for any clock cycle.
(j) after a period of time, the aveon switching architecture provides valid readdata, and the value of readdatavalid is reset.
(k) the main port captures the next unit (D2) of readdata on the rising edge of CLK ).
(l) the main port captures the final unit (D3) of readdata on the rising edge of the CLK ). The master port burstable read transmission ends.
4.9.3 abrupt transmission from the port

Burstcount is an input signal for avron slave port. Burst transmission not only affects burstcount behavior, but also affects the behavior of address, read, readdata, readdatavalid, write, writedata, and byteenable signals. The slave port can also use the input signal beginbursttransfer, which is sent by the aveon switching architecture in the first clock cycle of each burst transmission.
At the beginning of the burst transmission, the aveon switching architecture issues a valid address on the address, and the burstcount sends out the burst transmission length. For sudden transmission with the address a and the value of burstcount is B, B transmission is performed continuously from Port. Burst transmission ends after the data unit B is processed from the port.
For one burst transmission, the address is captured only once from the port. Burst transmission starts from the captured address, and the peripheral Logic infers all the remaining addresses in the burst transmission. The inferred address is related to whether the slave port uses local address alignment or dynamic address alignment:
If you use local address alignment, the address remains unchanged. For example, if the address is 0x1000 and the burstcount value is 0x0a, 10 data units are written to the unchanged address 0x1000.
If dynamic address alignment is used, each data unit transmitted increases by 1 from the port address. For example, if the address is 0x1000 and the burstcount value is 0x04, four data units are transmitted to the slave port address 0x1000, 0x1001, 0x1002, and 0x1003.
4.9.3.1 burst write transmission from the port

The burstable write transmission on the port is similar to the basic write transmission on the port. In addition to the burstcount, The avron switching architecture also sends chipselect, address, byteenable, writedata, and write signals. If the slave port is not ready for transmission, it is valid in the front waitrequest of the rising edge of the next CLK. Finally, the slave port sets waitrequest invalid, and captures the address and burstcount on the rising edge of the next CLK. The slave port also captures the first unit of writedata on the rising edge of the CLK. This is the only time to capture valid burstcount and address from the port.
When burstcount is greater than 1 from the port, follow the following rules:
If the value of burstcount is specified as N in the avron switching architecture, the slave port must accept N consecutive writedata data units to complete burst transmission. The arbitration between supported port pairs is locked until the end of the burst transmission, to ensure that data arrives in the order in which the master port initiates the burst transmission.
The slave port must capture writedata only when the write is valid. For the second or second data unit, the avron switching architecture can invalidate write on the rising edge of any CLK, indicating that it does not provide valid writedata. This will not terminate the burst transmission, but will only delay the burst transmission until the aveon switching architecture is enabled again.
The chipselect signal reflects write. When the avron switching architecture invalidates write, chipselect also invalidates.
The slave port can delay transmission by setting waitrequest to the rising edge of the CLK, which forces the aveon switching architecture to keep writedata, write, and byteenable unchanged in an additional period.
The aveon switching architecture is effective for all signal lines that set byteenable during burst transmission.

Burstable write transmission from the port

(a) The avron switching architecture generates the first unit of chipselect, address, burstcount, write, and writedata. In this example, the value of burstcount is 4.
(B) When waitrequest is set from the port, it indicates that it is not ready for handling burst transmission. In response, the aveon switching architecture keeps all output unchanged.
(c) it is invalid to set waitrequest from the port.
(d) capture the first unit (D0) of address, burstcount, write, and writedata on the rising edge of the CLK ). This is the only time to capture address and burstcount from the port.
(e) capture the next unit (D1) of writedata from the rising edge of the CLK ).
(f) If the write parameter is set for the aveon switching architecture, no valid writedata exists in this cycle.
(g) The writedata is not captured on the rising edge of the CLK because write is invalid.
(h) after a period of time, the aveon switching architecture again sets write and writedata as valid.
(I) capture the next unit (D2) of writedata from the rising edge of the CLK ).
(j) Valid waitrequest from the port. In response, the aveon switching architecture keeps all output unchanged throughout the clock cycle.
(k) An error occurred while setting waitrequest on the slave port.
(l) capture the final unit (D3) of writedata from the rising edge of the port CLK and end the burstable write transfer from the port.
4.9.3.2 burst read transmission from the port

Burst read transmission on the slave port is similar to that of the stream-line read transmission on the slave port with variable latency. Burstable read transmission has an obvious address and data phase, and the slave port uses the readdatavalid signal to indicate when it will provide valid readdata. The difference between the two lies in that a single burst address stage corresponds to multiple data stages.
In addition to the burstcount, The avron switching architecture also sends the chipselect, address, and read signals at the beginning of the burst read transmission on the port. If the slave port is not ready yet, the slave port is valid in the front waitrequest of the rising edge of the next CLK. Finally, the slave port sets the waitrequest to invalid, and captures the address and burstcount on the rising edge of the next CLK. The address stage ends. Multiple Data stages start.
When the burstcount value is greater than 1 from the port, follow the following rules:
If the value of burstcount is set to N in the avron switching architecture, N consecutive readdata data units must be generated from the slave port to complete burst transmission. The arbitration between master and slave Port Pairs remains locked until the burst transmission ends.
The slave port provides data units by issuing valid readdata and setting the readdatavalid to the rising edge of the CLK. If the value of readdatavalid is invalid, the burstable transmission will not be terminated, but the burstable transmission will be delayed until the slave port is reset to the value of readdatavalid.
During burst transmission, the aveon switching architecture is valid for all signal lines of byteenable.

Burstable read transmission from Port

(a) avron exchange architecture issues ddress, burstcount, and read. In this example, the value of burstcount is 4.
(B) In this example, if a valid waitrequest is set from the port, it indicates that it is not ready to handle the burst transmission. As a response, the aveon switching architecture will remain unchanged for all output periods.
(c) it is invalid to set waitrequest from the port.
(d) Capture address and burstcount from the rising edge of the CLK. The aveon switching architecture can start a new transmission on the rising edge of this CLK. (This is not the case in this example)
(e) This is the earliest clock rising edge that can return valid data from the port. In this example, the slave port does not send the readdatavalid, so the avron switching architecture does not capture readdata on the rising edge of this CLK.
(f) after a period of time, the slave port provides valid readdata and sets the value of readdatavalid.
(g) capture the first unit (D0) of readdata on the rising edge of the CLK ).
(h) capture the next unit (D1) of readdata on the rising edge of CLK ).
(I) the slave port does not have valid readdata, so it sets readdatavalid to invalid. Slave port can keep any cycle of readdatavalid invalid.
(j) after a period of time, the slave port provides valid readdata and sets the value of readdatavalid again.
(k) avron switching architecture captures the next unit (D2) of readdata on the rising edge of CLK ).
(l) capture the final unit (D3) of readdata on the rising edge of the CLK ). The burstable read transmission from the port ends.