Base of SVA (system OpenGL assertions)

1. What is assertions:

Assertions are based on the logic we have arranged in advance in the simulation process. If the assertions are successful, otherwise the assertions fail.

2 assertion execution is divided into: preparation (preponed) observation (observed) Response (reactive ).

3. assertion classification: Concurrent assertion (based on clock) and instant assertion (based on semantics ).

4sva (system defined logassertions): block creation:

Sequence:

Sequencename_of_sequence;

<Test expression>

Endsequence

 

Property name _ of _ Property

<Test expression>

Or

<Sequence>

Endproperty

 

Assertions _ name: assert property (property_name) ortest_expression;

Execution block:

Assertion_name:

Assertproperty (property_name)

<Success message>

Else

<Fail message>

Note: Keep the sequence independent from the clock. The attribute defines the clock as a good encoding style.

5 SVA detector steps:

Create a Boolean expression-> Create a sequence expression-> Create an Attribute-> assertion attribute;

6. Common statements and functions:

$ Rose (): detects the rising edge of a signal.

$ Fell (): Detection Signal descent edge

$ Stable (); checks whether the signal is stable.

# N: delay of N clock cycles.

# [N1: N2]: the delay is within the period from N1 to N2.

# [N1: $]: The latency is within the period from N1 to infinity.

Not: check if the property is not true (disable the property)

|->: If the first operator matches the operator detected in the same clock cycle

| =>: If the first operator matches the operator after the next clock cycle detection

Ended: end with a sequence as the connection point of Multiple sequences

XX? XX: the question mark expression is the same as that of C.

'Define true 1: Use a true expression to implement a series delay of N cycles.

$ Past (signal_name, number of clock cycles, [gating signal]): used to detect the values of logical expressions before n clock cycles.

Signalor sequence [* n] continuous repetition

Signal [-> N]: follows the repetition (there must be a signal after which the last repetition takes effect before the logical occurrence ).

Signal [= N]: non-continuous repetition. The number of repetitions is N.

And: The two sequences must have the same starting point.

Intersect: The two sequences must start at the same time and end at the same time.

Or: One of the sequences is successful.

If the time window is specified in the first_match: And or sequence, multiple matches may exist in the same test. First_match ensures that only the first sequence is used for matching.

Throughout :( expression) throughout (sequence definition) ensures that certain conditions remain true during detection.

Within: seq1 within seq2. Seq1 sequence Detection must be included at the start and end points of seq2.

Built-in system functions:

$ Onehot (expression): In any given clock edge, only one of the expressions is high.

$ Onehot0 (expression): one or none of them are high.

$ Isunknown (expression): checks whether any bit of the expression is X or Z.

$ Countones (expression): number of bits in the calculated vector.

Disable IFF (expression) <property definition>: if some conditions are true, no detection is performed.

Matched: it can be used to detect the end point of the first subsequence.

Secondary CT: a successful Property Test

<Cover_name>: cover property (property_name): number of attempts to be detected in the detection sequence; number of attribute successes; number of attribute failures; number of attribute successes empty.

 

7. Example:

Sequences32a;

@ (Posedgeclk)

((! A &&! B) #1 (C [-> 3]) #1 (A & B); // signal a and signal B are both low-level, after the delay of a clock, the system checks whether the signal C appears three consecutive high levels, and the last time C goes through a high-level clock delay signal a and signal B.

Endsequence

Sequences32b;

@ (Posedgeclk)

$ Fell (start) # [] $ rose (start); // The rising edge appears after 5-10 clock cycles starting from the descent edge of start. That is, start maintains 5-10 low clock cycles.

Endsequence

 

Sequence s32;

@ (Posedgeclk)

S32a within s32b; // The sequence s32a is contained in s32b, that is, the start and end points of the sequence s32b contain the start and end points of s32a.

Endsequence

 

Property p32;

@ (Posedgeclk)

$ Fell (start) |-> s32; // detect s32at the falling edge of start.

Endproperty

 

A32: assert property (p32 );

 

Base of SVA (system OpenGL assertions)