Basic concepts of time series analysis

In Quartus II, timing analysis is static timing analysis, that is, Stas (static timing analysis ). The object analyzed by STA is a synchronous logical circuit. The path is used to calculate the total latency and analyze the relative relationship between time sequences.

The most popular analysis tool in the industry is Primetime, which is based on Altera us.

 

STA is mainly for analysisFmax,Tsu,Th,TcoThese parameters. These parameters are defined as follows:

FMAX:Maximum clock frequency that can be achieved without violating the requirements for internal setup (tSU) and persistence (tH) time. It is the most important indicator in time series analysis and comprehensively shows the performance of the designed time series.

TSU:Before the trigger's clock edge arrives, the input data or the minimum time interval for enabling the signal to remain stable and unchanged. If not met, the data cannot be pushed into the trigger.

TH:When the trigger's clock edge arrives, the input data or the minimum time interval for enabling the signal to remain unchanged. If not met, the data cannot be pushed into the trigger.

TCO:The shortest time for the input signal from register D to Q after the clock signal changes on the input pin of the trigger (Register) device.

 

Graphical description of each parameter:

Fig1. relationship between tsu and th:

If the creation/persistence time is not met, the trigger may experience a sub-steady state. These two times are viewed on the entire path of the synchronous timing circuit. Tsu and th are two quantities related to slack.

Fig2.FMAXCalculation formula:

Fmax-maximum frequency of circuit operation; minimum cycle of tclk-circuit operation

Tco-latency from D to Q after Clock jump

Tdata-the latency caused by the combination logic itself

Tsu-trigger Creation Time

Tcik_skew-clock skew

 

Tco and Tsu are inherent latencies in the trigger. The typical value is 1 ~ 2ns, that is, mTco and mTsu in Quartus Handbook. It can be seen that only the delay of the combined Logical Circuit Between triggers can be shortened to increase the frequency of the synchronous time series circuit. Therefore, it is necessary to break down the large combination logic into smaller parts, and insert a trigger in the middle to increase the frequency of the circuit, which is the basic principle of the "Pipeline" technology.