Logic and computer design basics (formerly known as 4th)
Basic Information
Author: (US) mano. M.) (US) Kum (kime, C. R .)
Translator: Yan jishun
Series name: Computer Science Series
Press: Machinery Industry Press
ISBN: 9787111373117
Mounting time:
Published on: February 1, June 2012
Start: 16
Page number: 1
Version: 1-1
Category: computer more about"
Introduction
Computer books
Taking a general computer as the clue in logic and computer design basics (formerly known as version 4th), the author explains logic design, digital system design, and computer design in a simple and in-depth manner. Among them, Chapter 1 to Chapter 1st is the logic design, including the digital system and information, the combination logic circuit and its design, the arithmetic function block and the hardware description language and the time series circuit; chapter 1 to Chapter 2 provides an optional design topic for Digital System Design: data path, arithmetic logic unit, shift register, structure of a simple computer, single-cycle hard Link Control, multi-cycle hard link control, etc., register and register transmission and memory basis; chapter 2 to Chapter 2 is the computer design, including the computer design basics, instruction set structure, central processing units of the server, central processing units of the server, inputs, outputs, communications, and storage systems. The book contains 60 examples and problems from product design in modern daily life, which can stimulate the reader's interest in learning.
Logical and computer design basics (4th) can not only serve as an excellent teaching material for computer science, computer engineering, electronic technology, mechanical and electrical integration, and other students to learn hardware, it can also serve as an ideal reference for weak current engineers and computer science workers.
Directory
Logic and computer design basics (formerly known as 4th)
Publisher's words
Translator's preface
Preface
Chapter 1 digital system and information 1
1.1 indicates 2
1.1.1 digital computer 3
1.1.2 other computers 4
1.1.3 further description of general computer 7
1.2 digit 8
1.2.1 binary 9
1.2.2 octal and hexadecimal 10
1.2.3 number range 11
1.3 arithmetic operations 11
1.4 decimal code 15
1.5 character encoding 16
1.5.1ascii character encoding 16
1.5.2 check bit 18
1.6 Gray Code 18
1.7 Chapter 20
References 20
Exercise 21
Chapter 4 combined logic circuit 24
2.1 binary logic and logic gate 24
2.1.1 binary logic 24
2.1.2 logic gate 25
2.2 Boolean algebra 27
2.2.1 basic properties of Boolean algebra 28
2.2.2 algebraic processing 30
2.2.3 inverse function 32
2.3 Standard Format 32
2.3.1 minimum and minimum items 33
2.3.2 product 35
2.3.3 sum 36
2.4 Two-level circuit optimization 36
2.4.1 cost standard 37
2.4.2 Kano diagram structure 38
2.4.3 Karnov 40 of binary variables
2.4.4 carnov 41 with three variations
2.5 karnotu usage 43
2.5.1 primary implication items 43
2.5.2 non-prime primary implication item 45
2.5.3 product optimization 45
2.5.4 irrelevant minimum Item 46
2.6 procedural two-level optimization 48
2.7 multilevel circuit optimization 51
2.8 other door types 54
2.9 exclusive or operation and exclusive OR gate 57
2.10 high-impedance output 59
2.11 Chapter 60
References 60
Exercise 60
Chapter 1 Design of Combined logic circuit 65
3.1 Design Process 65
3.2 start hierarchical design 69
3.3 Process ing 71
3.4 verification 74
3.4.1 artificial logic analysis 74
3.4.2 simulation 75
3.5 combined function module 76
3.6 basic logical functions 76
3.6.1 fixed value, transmission and inverse 77
3.6.2 multiple-bit functions 77
3.6.3 enable 79
3.7 decoding 80
3.7.1 combination of decoder and enable 83
3.7.2 decoder-based combo circuit 84
3.8 encoder 85
3.8.1 priority encoder 85
3.8.2 expansion of encoder 87
3.9 select 87
3.9.1 multiplexing 87
3.9.2 multiplexing-based combo circuit 90
3.10 Chapter 92
References 92
Exercise 93
Chapter 2 arithmetic function block and hardware description language 99
4.1 iterative combo circuit 99
4.2 binary calculator 100
4.2.1 half-processors 100
4.2.2 full processors 100
4.2.3 binary traveling-wave carry-in calculator 101
4.3 binary subtraction 102
4.3.1 supplemental code 103
4.3.2 subtraction of binary complement 104
4.4 binary addition/subtraction operator 105
4.4.1 signed binary number: 106
4.4.2 addition and subtraction of signed binary numbers 107
4.4.3 spillover 108
4.5 other arithmetic function blocks 109
4.5.1 compression 110
4.5.2 increment by 111
4.5.3 decrease by 112
4.5.4 constant multiplication 112
4.5.5 division of constants 113
4.5.6 zero fill and symbol extension 113
4.6 Hardware Description Language 113
4.6.1 Hardware Description 114
4.6.2 logical synthesis 115
4.7 Hardware Description Language-vhdl116
4.8 Hardware Description Language-verilog123
4.9 summary of this chapter 129
References 129
Exercise 130
Chapter 1 Timing Circuit 5th
5.1 Definition of time series circuits 135
5.2 latches 137
5.2.1sr and s r latches 138
5.2.2d latches 140
5.3 trigger 141
5.3.1 master-slave trigger 141
5.3.2 edge triggered trigger 144
5.3.3 Standard graphical symbols 144
5.3.4 directly enter 146
5.4 timing circuit analysis 147
5.4.1 input equation 147
5.4.2 status table 148
5.4.3 state chart 150
5.4.4 timing circuit simulation 151
5.5 timing circuit design 152
5.5.1 design steps 153
5.5.2 construct the status chart and status table 153
5.5.3 status value assignment 158
5.5.4 Design of D triggers 159
5.5.5 Design of invalid status 161
5.5.6 verification 162
5.6 Other Types of triggers 164
5.7 state machine diagram and Its Application 166
5.7.1 state machine graph model 166
5.7.2 constraints of input conditions 168
5.7.3 Design and Application of the state machine diagram 169
5.8 HDL representation of the Time Series Circuit-vhdl175
5.9 The HDL representation of the Time Series Circuit-verilog180
5.10 summary of this chapter 184
References 185
Exercise 185
Chapter 2 selected design themes 6th
6.1 design space 193
6.1.1 integrated circuit 193
6.1.2cmos circuit process 194
6.1.3 process parameter 197
6.2 door propagation latency 198
6.3 trigger timing 199
6.4 timing circuit 201
6.5 Asynchronous interaction 202
6.6 synchronization and sub-steady state 203
6.7 synchronous circuit trap 208
6.8 programmable Implementation Technology 208
6.8.1 read-only memory (210)
6.8.2 programmable logical array 211
6.8.3 programmable array logical device 213
6.9 summary of this chapter 214
References 215
Exercise 215
Chapter 2 register and register transfer 7th
7.1 register and load enable 219
7.2 register transfer 222
7.3 register transfer operation 223
7.4 reminders for users of VHDL and OpenGL 225
7.5 micro-operation 225
7.5.1 arithmetic Microoperation 226
7.5.2 logical Microoperation 227
7.5.3 slight shift operation 228
7.6 microoperations on a single register 229
7.6.1 multiplexing-based transmission 229
7.6.2 shift register 231
7.6.3 traveling wave counter 234
7.6.4 synchronize binary counter 235
7.6.5 other type counters 238
7.7 register unit design 240
7.8 multi-register Transmission Based on multiplexing and bus 244
7.9 serial transmission and Microoperation 247
7.10 register transfer control 250
7.11 description of the shift register and counter's HDL -- vhdl262
7.12 description of the shift register and counter's HDL-verilog263
7.13 microprogram control 264
7.14 summary of this chapter 266
References 266
Exercise 266
Chapter 2 Storage Basics 8th
8.1 memory definition 273
8.2 Random Access Memory 273
8.2.1 read/write operations 274
8.2.2 timing waveform 275
8.2.3 memory feature 276
8.3sram integrated circuit 277
8.4sram chip array 281
8.5dram chip 283
8.5.1dram unit 284
8.5.2dram bit 285
8.6dram classification 288
8.6.1 synchronous DRAM (SDRAM) 289
8.6.2 double data rate SDRAM (ddr sdram) 290
8.6.3rambus DRAM (RDRAM) 291
8.7 dynamic RAM chip array 292
8.8 summary of this chapter 292
References 292
Exercise 292
Chapter 2 computer design basics 9th
9.1 Introduction 294
9.2 data path 294
9.3 arithmetic logic operation unit 297
9.3.1 arithmetic operation circuit 297
9.3.2 logical operation circuit 300
9.3.3 arithmetic logic operation unit 300
9.4 shift register 301
9.5 data path description 303
9.6 control words 305
9.7 a simple computer structure 309
9.7.1 Instruction Set 310
9.7.2 storage resource 310
9.7.3 Command Format 311
9.7.4 instructions 312
9.8 single-cycle hard Connection Control 314
9.8.1 command decoder 316
9.8.2 command and program example 317
9.8.3 single-cycle computers 319
9.9 multi-cycle hard Connection Control 319
9.10 summary of this chapter 328
References 328
Exercise 328
Chapter 2 instruction set structure 10th
10.1 concept of computer architecture 333
10.1.1 basic computer operation cycle: 334
10.1.2 register group 334
10.2 operand addressing 334
10.2.1 three-address command 335
10.2.2 two-address command 336
10.2.3 one-address command 336
10.2.4 zero-address instruction 336
10.2.5 addressing structure 337
10.3 addressing mode 339
10.3.1 implied mode 340
10.3.2 instant mode 340
10.3.3 indirect register and register mode 340
10.3.4 direct addressing mode 341
10.3.5 indirect addressing 342
10.3.6 addressing mode 342
10.3.7 addressing mode 343
10.3.8 addressing mode summary 343
10.4 instruction set structure 344
10.5 data transmission instructions 345
10.5.1 stack command 345
10.5.2 independent I/O and memory ing I/o346
10.6 data processing commands 347
10.6.1 arithmetic instruction 347
10.6.2 logic and bit processing commands 348
10.6.3 shift instruction 349
10.7 floating point calculation 350
10.7.1 arithmetic operation 350
10.7.2 shift code 351
10.7.3 standard operand format 351
10.8 program control command 353
10.8.1 condition branch command 354
10.8.2 process call and return command 355
10.9 program interruptions 356
10.9.1 interrupt type 357
10.9.2 external interrupt handling 357
10.10 summary of this Chapter 358
References 359
Exercise 359
Chapter 2 Central Processing Unit of the English version of 11th
11.1 pipeline data path 363
11.2 assembly line control 367
11.3 simplified instruction set computer 371
11.3.1 Instruction Set 371
11.3.2 addressing 373
11.3.3 data path Structure 374
11.3.4 control structure 376
11.3.5 data blocking 378
11.3.6 control blocking 383
11.4 Complex Instruction Set computers 386
11.4.1isa modify 387
11.4.2 data path modification 388
11.4.3 control unit change 389
11.4.4 microprogram control 391
11.4.5 Microprograms with complex commands 392
11.5 Other Related designs 395
11.5.1 high performance CPU concept 395
11.5.2 latest architecture innovation 397
11.6 summary of this Chapter 398
References 399
Exercise 400
Chapter 2 input, output, and communication 12th
12.1 computer I/O system 402
12.2 examples of peripherals 402
12.2.1 keyboard 402
403 hard drive
12.2.3 liquid crystal display 404
12.2.4i/o transmission rate: 406
12.3i/O interface 406
12.3.1i/O bus and interface parts 407
Example of 12.3.2i/O interface 408
12.3.3 allow 409
12.3.4 handshake 410
12.4 serial communication 411
12.4.1 synchronous transfer 412
12.4.2 further understanding of keyboard 412
12.4.3 package-based serial I/O bus 413
12.5 transmission mode 416
12.5.1 example of Program Control Transfer 417
12.5.2 interrupted transmission 417
12.6 interrupt priority 418
12.6.1 chrysanthemum chain priority 418
12.6.2 parallel priority circuit 420
12.7 Direct Memory Access 421
12.7.1dma control 421
12.7.2dma transmission 422
12.8 summary of this Chapter 423
References 424
Exercise 424
Chapter 1 storage system 13th
13.1 Hierarchical Storage System 426
13.2 local access 428
13.3cache memory 429
13.3.1cache ing 430
13.3.2 the row size is 435
13.3.3cache load 436
13.3.4 method 436
13.3.5 concept synthesis 437
13.3.6 command cache and data cache439
13.3.7 multilevel cache440
13.4 VM 440
13.4.1 page table 442
13.4.2 conversion backup buffer 443
13.4.3 virtual memory and cache445
13.5 summary of this chapter 445
References 445
Exercise 446
Index 448
Source of this book: China Interactive publishing network
