Block device driven 2--SD card driver 1 (sdchi.h analysis of linux-3.2.36) __linux

My experience:

Seeing some of the great God's instructions, I timidly entered the drivers/mmc/host/.

As the use of s3c2440, look at the driver, I will first find s3c words, so I noticed sdhci-s3c.c and S3CMCI.C.

Took a look at Kconfig

Config mmc_s3c
TriState "Samsung s3c SD/MMC card Interface Support"
Depends on arch_s3c2410
Help
This is selects a driver for the MCI interface found in
Samsung ' s s3c2410, s3c2412, s3c2440, s3c2442 CPUs.
If you are have a board based on one of those and a mmc/sd
Slot, say Y or M here.

If unsure, say N.

And look at makefile.

obj-$ (config_mmc_s3c) + + S3CMCI.O

I think I can use the S3CMCI. I guess S3cmci and sdhci-s3c are different chips. But when I look at the code, it's not exactly like that.

Remember the great God said struct mmc_host. The main structure used by SD driver, but sdhci-s3c used is struct sdhci_host.

What is the situation.

First I think about what SDHCI is, and I see that all the SDHCI-*.C drivers are using SDHCI.C, and I see SDHCI.C offsets to register operations

Is the same, so I thought of the USB Ochi drive. There should be a protocol that the SD controller follows.

And then I opened up s3c6410 's datasheet.

The first line of SD Standard host is dazzling. Finally, I found this in Baidu:

Part_a2_sd_host_controller_simplified_specification_ver2.00.pdf

This is what is said to be the agreement, SDHCI.C to achieve things. S3C2440 does not follow this.

First look at the SDHCI, see C before you read. h file analysis

* * linux/include/linux/mmc/sdhci.h-secure Digital Host Controller Interface * * Copyright (C) 2005-2008 Pierre Os
 Sman, all Rights Reserved. * * this are free software; Can redistribute it and/or modify * it under the terms of the GNU general public License as published by * Software Foundation;
 Either version 2 of the License, or (at * your option) any later version. * * #ifndef linux_mmc_sdhci_h #define LINUX_MMC_SDHCI_H #include <linux/scatterlist.h> #include <linux/ compiler.h> #include <linux/types.h> #include <linux/io.h> #include <linux/mmc/host.h> struct  Sdhci_host {/* Data set by hardware interface driver */const char *hw_name;/* Hardware bus name///hardware buses name unsigned	int quirks; /* deviations from spec.//deviation specification//We see what quirks and how the code will handle/* Controller doesn ' t honor resets unless we touch the clock Regi Ster * * * #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)/* Sdhci_quirk_clock_before_reset is some to set the clock before resetting the storageThe device will call Host->ops->set_clock (host, clock) before the reset, and the driver provides/////////////////Controller has bad caps bits, but really, supports Ine SDHCI_QUIRK_FORCE_DMA (1<<1)/* if (Host->quirks & SDHCI_QUIRK_FORCE_DMA) host
->flags |= SDHCI_USE_SDMA; Support SDMA *////////////Controller doesn ' t like to be reset when there are no card inserted.
* * #define SDHCI_QUIRK_NO_CARD_NO_RESET (1&LT;&LT;2)/* Above in English has said very clearly: No card insertion, the controller does not want to reset.
When you encounter this standard when you reset, you will want to try to read the current state, return successfully, and fail to reset. */////////* Controller doesn ' t like Clearing's power reg before a change * * * #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1&LT;&L
T;3)/* The controller does not want to clear the power register before a change mmc_vdd.
Encounter this, directly change the power register value, do not clear. *//////* Controller has flaky internal state so reset it to each iOS change/#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1
&LT;&LT;4)/* is used in Sdhci_do_set_ios ().
Explanation: Some controllers go crazy in some operations, even CMD0, and the solution is to reset each iOS.  */* Controller has an unusable DMA engine//#define SDHCI_QUIRK_BROKEN_DMA (1&LT;&LT;5)//controller has an unusable DMA engine//SDMA: Secure DMA//adma:advanced DMA/* Controller has an unusable ADMA engine/#define SDHCI_QUIRK_BROKEN_ADMA (1&LT;&LT;6)//controller has an inability to Use of the ADMA engine/* Controller can only DMA from 32-bit aligned addresses/#define SDHCI_QUIRK_32BIT_DMA_ADDR (1&LT;&LT;7)/			/DMA to 32-bit address alignment/* Controller can only DMA chunk sizes that are a multiple of bits */#define Sdhci_quirk_32bit_dma_size (1<<8) The size of the//DMA is a multiple of 32/* Controller can only ADMA chunks that are a multiple of bits */#define SDHCI_QUIRK_32

The Bit_adma_size (1<<9)//ADMA size is a multiple of 32//encounters these address and size limits and will first determine the data. /* Controller needs to being reset after each request to stay stable * * * #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<1 0//After each request the controller needs to be reset to remain stable/* in sdhci_tasklet_finish (), i.e. when the task is completed, when Host->quirks & Sdhci_quirk_reset_after_
When request is set up, perform the reset. *////* Controller needs voltage and Power writes to happen separately */#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1&L
T;&LT;11)/* This standard is to turn on the power, to set the voltage first. Marvell Cafe's chip is so code, first set, then or on sdhci_power_oN Open if (Host->quirks & Sdhci_quirk_no_simult_vdd_and_power) sdhci_writeb (host, PWR, sdhci_p

        Ower_control);

        PWR |= sdhci_power_on;

Sdhci_writeb (host, PWR, Sdhci_power_control); */* Controller provides an incorrect timeout value for transfers/#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<
12)//The controller provides an incorrect timeout value.
        /* will use 0xE as a timeout. That's to make the hardware have a long timeout, better than the short one.
if (Host->quirks & Sdhci_quirk_broken_timeout_val) return 0xE; *///* Controller has an issue with buffer bits for small transfers/#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13
//Controller support for small byte transmission///Some controllers (e.g. JMicron jmb38x) scrambling the transmission bit, (less than 4 bytes).
As long as it has a block, we can ignore these bits. The 11th bit (buffer read enable) of the Register prnsts (s3c6410 has this register) is ignored/* Controller does not provide transfer-complete when n OT busy */#define SDHCI_QUIRK_NO_BUSY_IRQ (1&LT;&LT;14)//When busy, the controller does not provide transmission complete interrupt//If busy, Linux will execute the following code/* if (INTM Ask & Sdhci_int_response) Sdhci_fInish_command (host); */* Controller has unreliable card detection//#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1&LT;&LT;15)//Unreliable cards detection/* s The Dhci_set_card_detection () function will judge the return: if (Host->quirks & sdhci_quirk_broken_card_detection) ret
Urn */* Controller reports Inverted Write-protect State/#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1&LT;&LT;16)/* Report counter
                Write-protected status value: Sdhci_check_ro () function: Return Host->quirks & Sdhci_quirk_inverted_write_protect?
!is_readonly:is_readonly; */* Controller has nonstandard clock management//#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1&LT;&LT;17)//non-standard clock management//non-standard Yes, you can do it yourself/* Sdhci_set_clock () if (Host->ops->set_clock) {Host->ops->set_clock (host, clock)
                ;
        if (Host->quirks & Sdhci_quirk_nonstandard_clock) return; } *//////* Controller does not like fast PIO transfers/#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<&LT;18)//pio need to delay//delay to give him a delay/* SDHCI_TRANSFER_PIO () if (Host->quirks & Sdhci_quirk_pio_needs_delay
) Udelay (100); * * * Controller losing Signal/interrupt Enable states after reset * * */#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1&lt &LT;19)//reset will lose signal/interrupt enable state/* in Sdhci_reset (), read out the interrupt enabling state if (Host->quirks & Sdhci_quirk_restore_irqs_after_
RESET) Ier = Sdhci_readl (host, sdhci_int_enable); Reset and then set the IF (Host->quirks & Sdhci_quirk_restore_irqs_after_reset) Sdhci_clear_set_irqs (host
, Sdhci_int_all_mask, IER); */////* Controller has to is forced to the use block size of 2048 bytes/#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20 //Controller is forced to use 2048-byte block size/* if (Host->quirks & sdhci_quirk_force_blk_sz_2048) {MMC-&GT;MAX_BL
K_size = 2; *////* Controller cannot do multi-block transfers//#define SDHCI_QUIRK_NO_MULTIBLOCK (1&LT;&LT;21)//not multi-block processing/* sdhci_a D//maximum block count in D_host (). Mmc->max_blk_count = (Host->quirks & sdhci_quirk_no_multiblock)?
1:65,535;
You can look at spec, there are three kinds: single block, Multi blocks, Infinite block. */* Controller can only handle 1-bit data transfers//#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1&LT;&LT;22)//One-bit data transfer// Not 1-bit on 4-bit/* if (!
Host->quirks & Sdhci_quirk_force_1_bit_data)) Mmc->caps |= Mmc_cap_4_bit_data;
Before this code there is a sentence: A controller can support 8-bit width, but the board itself may not pin out. Board support 8-bit width must be set "Mmc->caps |= Mmc_cap_8_bit_data" before its own platform code calls Sdhci_add_host (); 8-bits is not the same code handling for Sdhci_
OPS platform_8bit_width (function pointers) are handled by themselves. */* Controller needs 10ms delay between applying power and clock/#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<2
                3)//Set the power and clock between the 10ms delay/* Sdhci_set_power () if (Host->quirks & Sdhci_quirk_delay_after_power)
Mdelay (10); */* Controller uses SDCLK instead of TMCLK for data timeouts */#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1&LT;&LT;24)///SDCLK instead of TMCLK as data timeout//SDCLK is SD bus clock//TMCLK is specifically designed to detect timed out clocks/* Controller reports wrong base clock capability * * #define Sdhci_quirk_cap_clock_base_broken (1&LT;&LT;25)//Basic Clock function Error */if (HOST-&GT;MAX_CLK = 0 | | host->quir  KS & Sdhci_quirk_cap_clock_base_broken) {if (!host->ops->get_max_clock) {Pr_err ("%s:hardware doesn ' t specify base Clock" "frequency.\n"
                        , Mmc_hostname (MMC));
                Return-enodev;
        } HOST-&GT;MAX_CLK = Host->ops->get_max_clock (host); You can see that MAX_CLK is 0 o'clock and we can get///////* Controller cannot support end Attribute in NOP ADMA by Host->ops->get_max_clock ()
                Iptor/#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1&LT;&LT;26)//does not support NOP ADMA Properties/* in Sdhci_adma_table_pre () If this flag is not invoked
NOP, end, valid SDHCI_SET_ADMA_DESC (DESC, 0, 0, 0x3); * * * Controlleris missing device caps.
        Use caps provided by host */#define SDHCI_QUIRK_MISSING_CAPS (1&LT;&LT;27)//missing device caps, using the host's caps/* Sdhci_add_host () Caps[0] = (Host->quirks & sdhci_quirk_missing_caps)?
Host->caps:sdhci_readl (host, sdhci_capabilities); */* Controller uses Auto CMD12 command to stop the transfer * * * #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28
In//spec, the Auto CMD12 (Stop command)/* will eventually be written to the register via mode Sdhci_writew (host, mode, Sdhci_transfer_mode); */* Controller doesn ' t have hispd bit field in Hi-speed SD card/#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)//No
There is hispd bit//This will be written through CTRL/* SDHCI_WRITEB (Host, CTRL, Sdhci_host_control); *////* Controller treats ADMA descriptors with length 0000h incorrectly */#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (
                        1&LT;&LT;30///Length 0 Adam descriptor is considered incorrect//if (Host->quirks & Sdhci_quirk_broken_adma_zerolen_desc)
                Mmc->max_seg_size = 65535;else mmc->max_seg_size = 65536; This max_seg_size is done by the scatter/aggregate is each entry cannot be greater than 64k/* * The read-only detection via sdhci_present_state Register is unstable */#define S
        Dhci_quirk_unstable_ro_detect (1&LT;&LT;31)//through the Present_state register detection read-only is not allowed//if such a multiple detection/* ro_count = 0; for (i = 0; i < Sample_count i++) {if (Sdhci_check_ro (host)) {if (++ro
                _count > SAMPLE_COUNT/2) return 1;
        } msleep (30);	} * * unsigned int quirks2; /* More deviations from spec. */#define SDHCI_QUIRK2_OWN_CARD_DETECTION (1<<0)//own card detection/* and above Sdhci_quirk_broke		N_card_detection the same * */int IRQ;	/* Device IRQ */void __iomem *ioaddr;	/* Mapped address/const struct SDHCI_OPS *ops;             /* Low Level HW interface/* is mainly hardware operating interface struct Sdhci_ops {#ifdef config_mmc_sdhci_io_accessors u32 (*read_l)
     (struct sdhci_host *host, int reg);   U16 (*read_w) (struct sdhci_host *host, int reg);
        U8 (*read_b) (struct sdhci_host *host, int reg);
        void (*write_l) (struct Sdhci_host *host, u32 val, int reg);
        void (*write_w) (struct Sdhci_host *host, U16 val, int reg);
void (*write_b) (struct Sdhci_host *host, U8 val, int reg);              #endif above you do not set up to use the kernel provided readl equal void (*set_clock) (struct sdhci_host *host, unsigned int clock);/Set Clock int (*ENABLE_DMA) (struct sdhci_host *host);//enable DMA unsigned int (*get_max_clock) (struct sdhci_host *host);//Get maximum clock Unsig Ned Int (*get_min_clock) (struct sdhci_host *host)//get min clock unsigned int (*get_timeout_clock) (struct SDHCI_HO
                                               St *host);/Get timeout clock int (*platform_8bit_width) (struct sdhci_host *host,
           int width);//eight-bit transport operation Void (*platform_send_init_74_clocks) (struct sdhci_host *host,                                  U8 Power_mode)//only in sdhci-pxav3.c see Use, do not know why unsigned int (*get_ro) (struct SDHC I_host *host);/Get readonly State Void (*platform_reset_enter) (struct sdhci_host *host, U8 Mask);//reset before processing VO ID (*platform_reset_exit) (struct sdhci_host *host, U8 Mask);//after reset processing int (*set_uhs_signaling) (struct sdhci_

Host *host, unsigned int uhs);//uhs:ultra high Speed set ultra-high speed signal void (*hw_reset) (struct sdhci_host *host);//reset};	* * struct regulator *VMMC;	/* Power Regulator *////* Internal data */struct mmc_host *mmc;		/* MMC structure///famous MMC structure u64 dma_mask; /* Custom DMA Mask */#if defined (config_leds_class) | |	Defined (config_leds_class_module) struct Led_classdev led;
/* LED control */char led_name[32];	#endif spinlock_t Lock;		/* MUTEX */INT flags; 	/* Host attributes */#define SDHCI_USE_SDMA (1<<0)/* Host is SDMA capable/#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable * * * #deFine SDHCI_REQ_USE_DMA (1&LT;&LT;2)/* Use DMA for this REQ. */#define SDHCI_DEVICE_DEAD (1<<3)/* DEVICE unrespons  ive * * * #define SDHCI_SDR50_NEEDS_TUNING (1<<4)/* SDR50 NEEDS Tuning/#define SDHCI_NEEDS_RETUNING (1<<5)/* Host needs retuning * * * #define SDHCI_AUTO_CMD12 (1<<6)/* AUTO CMD12 Support/#define SDHCI_AUTO_CMD23 (1<< 7)/* Auto CMD23 Support * * * #define SDHCI_PV_ENABLED (1<<8)/* Preset value ENABLED */#define Sdhci_sdio_irq_enable	D (1<<9)/* SDIO IRQ enabled/unsigned int version;	/* SDHCI spec. version *///, currently 1.0 2.0 3.0 unsigned int max_clk;	/* Max possible freq (MHz) */unsigned int timeout_clk;	/* Timeout freq (KHz) */unsigned int clk_mul;	/* Clock muliplier value */unsigned int Clock;			/* Current Clock (MHz) */U8 PWR;	/* Current voltage * * BOOL runtime_suspended;	/* Host is runtime suspended *//Hang flag struct mmc_request *mrq;	/* Current request */struct Mmc_command *cmd; /* Current command */StruCT Mmc_data *data;	/* Current Data request */unsigned int data_early:1;	/* Finished before CMD *///data management completes struct Sg_mapping_iter sg_miter before the command is completed;	/* SG state for PIO *///sg status unsigned int blocks;		/* Remaining PIO blocks///remaining PIO blocks int sg_count;		/* Mapped SG entries *///map number of SG items U8 *adma_desc;	/* ADMA Descriptor Table *///AMDA descriptor U8 *align_buffer;	* Bounce buffer///rebound buffer dma_addr_t adma_addr; /* Mapped ADMA descr.	Table */dma_addr_t align_addr;	/* Mapped Bounce buffer */struct tasklet_struct card_tasklet; /* Tasklet Structures/* Interrupt function: if (Intmask & Sdhci_int_card_insert |
    Sdhci_int_card_remove)) will invoke Tasklet_schedule (&host->card_tasklet); 
    Can be seen is the processing card inserts and remove, the corresponding function is Sdhci_tasklet_card () * * struct tasklet_struct finish_tasklet;
	/* Sdhci_remove_host () function, if HOST-&GT;MRQ is not null.
    Will call Tasklet_schedule (&host->finish_tasklet); It can be seen that there is a request when the SD is removed to perform the processing, the corresponding function sdhci_tasklet_finish (); * * struct timer_list timer;	/* Timer for Timeouts *///Timeout timer unsigned int caps;	/* Alternative capabilities *///alternative function unsigned int ocr_avail_sdio;
	/* The OCR bit masks///OCR registers record the supported voltage unsigned int ocr_avail_sd;

	unsigned int ocr_avail_mmc; The CMD19 is reserved in SD spec.	In Sdhci v3.00, a tuning command is used to wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer read Ready interrupt * * SDHCI_DATA_IRQ ()//CMD19 generates _ONLY_ Buffer read Ready Inter
                Rupt if (Intmask & Sdhci_int_data_avail) {if (Sdhci_get_cmd (SDHCI_READW (host, sdhci_command)) = =
                    Mmc_send_tuning_block) {host->tuning_done = 1;
                    WAKE_UP (&host->buf_ready_int);
            Return	The Wake function is sdhci_execute_tuning ()/unsigned int tuning_done;	/* Condition flag set when CMD19 succeeds *///CMD19 success flag unsigned int tuning_count;	/* Timer count for re-tuning *///tuning timing unsigned int tuning_mode; /* RThe e-tuning mode supported by host *///tuning pattern supports #define SDHCI_TUNING_MODE_1 0 struct timer_list tuning_timer;
/* Timer for tuning *///tuning timer unsigned long private[0] ____cacheline_aligned;
};
 #endif/* Linux_mmc_sdhci_h * *