Brief Introduction to powerpc

Advantages of PowerPC over arm:

With its outstanding performance and high integration and advanced technology, PowerPC chips are used in network communication applications, industrial control applications, home digitalization, network storage, military fields, power System Control is widely used. because PowerPC is cheaper than arm devices

Tools are pirated everywhere, so PowerPC is not very popular in China. however, it is widely used in some countries in Europe and the United States. If you do not study PowerPC in the communication Major of colleges and universities, it should be an important mistake for colleges and universities. I personally think that PowerPC has the following advantages over arm: 1. High Integration

As well as advanced technology, The Freescale PowerPC processor is now integrated with USB, PCI, DDR controller, Sata controller, Gigabit network port controller, CAN controller, rapidio, pci_express controller, and ieee1588 communication protocol, supports CPM coprocessor, DMA, SPI, And I protocols for various communication protocols.

2c. UART, etc., customers do not need to design complex peripheral circuits, reduce design complexity and use of materials, arm is not as good as second, the chip range is large, high performance, easy to upgrade, from 50m-1.7g, there are processors, and PowerPC will be like multi-core processors, such as the introduction of integrated dual-core

E500 core mpc8572, MIPS performance up to 6897, arm I don't think the frequency is 1g, arm is about 1.1 MIPS/MHz, power architecture is greater than 2.0 MIPS/MHz, therefore, PowerPC occupies a large proportion of high-end embedded applications, and arm is not comparable.

In terms of development difficulty, in fact, PowerPC processor development is not very difficult, but because there are few developers, there are relatively few Chinese materials, and development tools are not as pirated as arm, some people complain that it is difficult to develop the PowerPC processor, such as Freescale.

Datasheet, detailed design documents for users, and the underlying driver, freesclae has been developed. you can ask a question on their forum or send an email to the technical support staff. They can reply quickly. I believe there will be more and more people in the future. 4. in terms of price, some people complain about the PowerPC location.

The processor is expensive, which may be more expensive than arm at the same frequency. However, for MIPS/MHz Performance Comparison and integrated peripheral circuits, PowerPC still has some advantages, freescale is also aware of this problem, so it has launched the following low-frequency mpc8313 and mpo8323

Price processors, and low-price processors such as ColdFire are also available. As Freescale products continue to launch, the price of PowerPC processors will become cheaper and cheaper.

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PowerPC memory management model (MMU)
The MMU specifications are largely provided by the OEA. The primary functions of the MMU are
Translate logical (valid) addresses to physical addresses for memory accesses and I/O accesses (most
I/O accesses are assumed to be memory-mapped), and to provide access protection on a block or page
Basis. Note that your aspects of memory management are implementation-dependent. The description in
Chapter 7, "memory management," describes the conceptual model of a MMU; however, Processors may
Differ in the specific hardware used to implement the MMU model.
Processors require address translation for two types of transactions-instruction accesses and Data
Accesses to memory (typically generated by load and store instructions ).
The memory management specification between des models for 32-bit implementations. the MMU of a 32-bit
Processor provides 232 bytes of logical address space accessible to supervisor and user programs with
4-kbyte page size and 256-mbyte segment size.
In 32-bit implementations, the entire 4-gbyte memory space is defined by sixteen 256-mbyte segments.
Segments are configured through the 16 segment registers.
The block address translation (BAT) mechanic maps large blocks of memory. block sizes range from
128 Kbytes to 256 Mbytes and are software-selectable. In addition, the MMU of 32-bit processors uses
Interim virtual address (52 bits) and hashed page tables in the generation of 32-bit physical addresses.
Two types of processor-generated accesses require address translation: instruction accesses and Data
Accesses to memory generated by load and store instructions. The address translation mechanic is
Defined in terms of segment tables (or segment registers in 32-bit implementations) and page tables used
To locate the logical-to-physical address mapping for instruction and Data Accesses. The segment
Information translates the logical address to an interim virtual address, and the page table information
Translates the virtual address to a physical address.
Translation lookaside buffers (tlbs) are commonly implemented to keep recently-used page table entries
On-Chip. Although their exact characteristics are not specified by the architecture, the general concepts that
Are pertinent to the system software are described.
The block address translation (BAT) mechanic is a software-controlled array that stores the available
Block address translations on chip. Bat array entries are implemented as pairs of BAT registers that are
Accessible as supervisor SPRS; refer to Chapter 7, "memory management," for more information.

 

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PowerPC interrupt Model
The interrupt mechanic, defined by the OEA, allows the processor to change to supervisor state as
Result of external signals, errors, or unusual conditions arising in the execution of instructions. When
Interrupts occur, information about the state of the processor is saved to varous registers and the processor
Begins execution at an address (interrupt vector) predetermined for each type of Interrupt. interrupt handler
Routines begin execution in supervisor mode. The interrupt model is described in detail in chapter 6,
"Interrupts." Note also that some aspects regarding interrupt conditions are defined at other levels of
Architecture. For example, floating-point exception conditions are defined by the uisa, whereas
Interrupt mechanic is defined by the OEA.
The architecture requires that interrupts be handled in program Order (excluding the optional floating-point
Imprecise modes and the reset and machine check interrupt); therefore, although a particle
Implementation may recognize interrupt conditions out of order, they are handled strictly in order. When
An instruction-caused interrupt is recognized, any unexecuted instructions that appear earlier in
Instruction stream, including any that have not yet begun to execute, are required to complete before
Interrupt is taken. Any interrupts caused by those instructions must be handled first. Likewise, interrupts
That are asynchronous and precise are recognized when they occur, but are not handled until all instructions
Currently executing successfully complete processing and report their results.
The OEA supports four types of interrupts:
? Synchronous, precise
? Synchronous, imprecise
? Asynchronous, Maskable
? Asynchronous, nonmaskable

 

Brief Introduction to powerpc