Brief Introduction to ssram, SDRAM, and Flash

Abstract
The problem of capacity calculation is encountered when debugging the SDRAM using the nio ii. The following is an introduction:
Introduction
Question 1: What are dram, SRAM, and SDRAM?
A: The terms are explained as follows:
DRAM -------- the dynamic access device immediately. data can be stored only after constant refreshing, and the row and column addresses are reused. Many of them have page modes.
SRAM -------- static random memory. When powered on, data does not need to be refreshed, and data will not be lost. It is generally not reused by row and column addresses.
SDRAM ------- synchronous DRAM, that is, Data Reading and Writing requires clock synchronization.

Question 2: Why is DRAM refresh and SRAM unnecessary?
A: This is determined by the ram design type. DRAM uses a T and an RC Circuit, resulting in leakage and slow discharge of capacitors. Therefore, it is necessary to refresh frequently to store data.

Question 3: What is memory used? What is the relationship between these three products and our actual use?
A: memory (I .e. random Memory RAM) can be divided into static random memory SRAM and dynamic random Memory DRAM. We often say"
Memory refers to dram. But there is little access to SRAM.

Question 4: why is there a small amount of DRAM used?

A: 1) because the high cost of making SRAM with the same capacity is much higher than that of DRAM, the development of the same capacity is limited. Therefore, SRAM is only used for the level-1 cache inside the CPU and the built-in level-2 cache. Only a small number of network servers and routers can use SRAM.

2) Different Storage unit structures lead to different capacities: a dram storage unit requires a transistor and a capacitor (not
Including a row-read-out amplifier), and an SRAM storage unit requires about six transistors. DRAM and SDRAM due to implementation process problems, capacity
The read/write speed is not as high as that of the SRAM.

Question 5: What are the characteristics of the most used dram? What is the process? (Memory is Dram)

A: 1) DRAM requires periodic refresh operations. We should not confuse SRAM with read-only memory (ROM) with flash memory because SRAM is a kind of volatile memory, it can maintain data only when the power supply is continuously supplied. "Random Access" means that the content of the memory can be accessed in any order, regardless of the location of the previous access.

2) DRAM and SDRAM have a large capacity due to technical issues. However, the speed of reading and writing is not as high as that of SRAM, but now the speed of SDRAM is also very fast, and the clock seems to have been 150 MB. The read/write cycle is smaller than 10ns.

3) The actual throughput is reduced despite the high frequency of SDRAM operation. Taking pc133 as an example, the clock cycle of pc133 is 7.5ns. When CAS latency is 2, it needs to complete 8 burst read operations in 12 cycles and 8 burst write operations in 10 cycles. However, if you access the bank in an alternate way, the SDRAM can perform a read/write operation in each cycle (except for the refresh operation, of course ).

4) In fact, the current mainstream high-speed memory is ssram (synchronous SRAM) and SDRAM (synchronous DRAM ). Currently, the maximum capacity of ssram that you can buy is 8 Mb/piece, and the maximum operating speed is 166 MHz. The maximum size of the SDRAM that you can buy is 128 MB/piece, the maximum operating speed is 133 MHz.

Question 6: It is used less quickly. What are the characteristics of the SRAM used for server cache?

Answer: 1) the SRAM is static, the dram or SDRAM is dynamic, and the static one is The bistability trigger to store information, while the dynamic one is the electronic, refresh from time to time. Static random access memory is a type of semiconductor memory. Static means that data stored in SRAM will not be lost if no power is lost.

2) SRAM is actually a very important memory, and it is widely used. The speed of SRAM is very fast, and data integrity can be maintained during fast reading and refreshing. The internal structure of the SRAM uses a bi-stable circuit to store data. The circuit structure of SRAM is very complex.

3) from the transistor type, SRAM can be divided into bipolar and CMOS. In terms of functions, SRAM can be divided into asynchronous SRAM and synchronous SRAM (ssram ). Asynchronous SRAM access is independent of the clock, and data input and output are controlled by address changes. All accesses to the synchronized SRAM are started along the rise/fall of the clock. Address, data input, and other control signals are related to clock signals.

One thing to note:
SRAM should not be confused with SDRAM, which represents synchronous DRAM, which is totally different from SRAM. It should not be confused with psram. psram is a dram disguised as SRAM.
 
Logical bank and chip capacity representation of SDRAM
1. Logical bank and Chip Width
After explaining the external form of the SDRAM, we should have a deep understanding of the internal structure of the SDRAM. The main concept here is the logical bank. Simply put, the internal structure of SDRAM is a storage array. Because it is a pipe-type storage (such as queuing to buy tickets), it is difficult to achieve random access.
The array is like a table. You can fill in the data as a table. Like table search, you can specify a row and a column to find the expected cells accurately, this is the basic principle of memory chip addressing. For memory, this cell can be called a storage unit. What is the name of this table (storage array? It is a logical Bank (L-bank ).

L-bank storage array

Because of technology, cost, and other reasons, it is impossible to make only one full-capacity L-bank, and most importantly, due to the limitation of the working principle of SDRAM, A single L-bank will cause very serious addressing conflicts and significantly reduce memory efficiency (this will be detailed later ). Therefore, we split the data into multiple L-banks in the SDRAM, which were two in the past and are basically four at present. This is also the maximum number of L-banks in the SDRAM specification. Up to 32 RDRAM instances are supported. In the latest DDR-ⅱ standard, the number of L-banks is increased to 8.
In this way, you must first determine the L-bank, and then select the corresponding row and column in the selected L-bank for addressing. It can be seen that the access to the memory can only be one L-bank at a time, and the data exchanged with the North Bridge each time is the capacity of a "storage unit" in the L-bank storage array. In some manufacturers' statements, the storage unit in L-bank is called word (here represents the set of bits rather than the set of bytes ).
As we can see from the past, the data size of the memory chip in one transmission rate is the chip Bit Width, so the capacity of this storage unit is the chip Bit Width (also the L-bank bit width, this relationship is only valid for SDRAM. The reason is described below.

2. memory chip capacity
Now we should be clear about the basic organizational structure of the memory chip. How is the memory capacity calculated? Obviously, the memory chip capacity is the total capacity of all l-banks. The method for calculating the number of storage units is the same as that for calculating the number of units in a table:
Number of storage units = number of rows × Number of columns (to obtain the number of storage units for an L-bank) × Number of L-Banks

We can see that row = 13 column = 9 bank = 4 data width = 32
I made a ridiculous mistake in calculating the number of storage units. The calculation result is different from the size shown above:
468 (number of storage units) = 13 (number of rows) × 9 (number of columns) (obtain the number of storage units for an L-bank) × 4 (number of L-Banks)
The resulting capacity is much different from 64 bytes.
The correct calculation should be as follows:
Number of rows = 2 ^ 13 columns = 2 ^ 9
Capacity = 2 ^ 13x2 ^ 9x4x32/1024/1024/8 = 512 Mbits = 64 Mbytes

In many memory product introduction documents, the capacity of the chip (or the chip specifications/organizational structure) is expressed in the m × w mode ). M is the total number of storage units in the chip. The unit is MB (M in short, with an exact value of 1048576 instead of 1000000). W represents the capacity of each storage unit, that is, the bit width of the SDRAM chip. The unit is bit. The calculated chip capacity is also measured in bytes. However, you can convert the size by dividing by 8 to byte ). For example, 8 m × 8 is an 8-bit wide chip with 8 m storage units with a total capacity of 64 Mbit (8 Mb ).

However, m × W is the simplest representation method. It is a company's representation of its memory chip capacity, which can be said to be one of the most formal forms.

Industry-standard memory chip capacity Representation

after calculation, we can find that the capacity of these three specifications is 128 Mbits, but the change in BIT width leads to a change in the number of storage units. From this example, we can also see that in the same total capacity, the bit width can adopt a variety of different designs.
3. dimm design related to chip bit width
Why are there many different bit widths under the same total capacity? This is mainly to meet the needs of different fields. Now we know that the Bit Width of p-bank is fixed. That is to say, when the bit width is determined, the number of chips in a p-bank is naturally determined, as mentioned above, p-bank has requirements on the bit width of the chip set and has no restrictions on the capacity of the chip set. High-bit-width chips make the design of dimm simpler (because few chips are used). However, when the chip capacity is the same, the capacity of such dimm will certainly be inferior to that of modules using low-bit-width chips, because the latter can accommodate more chips in a p-bank. For example, in the above memory chip capacity identification diagram, the capacity is 128 Mbit, which is 16 Mb. If dimm is designed with a dual-p-bank + 16-bit chip, it can only accommodate 8 Chips, 128 MB. However, if a 4-Bit Width chip is used, the chip can accommodate 32 chips, which is 512 MB. The size of the dimm varies by 4 times, which indicates the importance of the chip width on the design of the dimm. Therefore, the 8-bit wide chip is a good choice between the capacity and cost balance on the desktop, so it is also the most popular in the market, and the chip higher than the 16-Bit Width is generally used in the case of larger width, for example, for graphics cards, the 4-Bit Width chip is obviously very suitable for large-capacity memory applications, basically not in the standard unbuffered module design.
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