Building FPGA Engineering

1, kneeling ask the program compiled by VHDL How to generate after the compilation. The schematic diagram of the BDF format EDA design has many modules how to integrate each module to imitate

Quartus II in the file directory creat/update, and then creat symbol files for the current file can generate the module, and then create a new BDF file, double-click the space, will jump out of the dialog box, add the module you want.
EDA Design has many modules how to integrate each module to imitate? This problem should be your program only sub-modules, no top-level module, write a top-level module, you can integrate to simulate ....

2, in Qautus II in the top-level document with schematic, sub-module with Verilog HDL language description, how to achieve this?

Just build a schematic file in Quartus as a top-level file. Then build the Verilog file, do not compile, after writing the program, from the file-create/update create symbol files for the current file, the general meaning is to convert the written Verilog (. v) file into a schematic (. BDF), and then add the diagram to the schematic selection library when it's done!

Building FPGA Engineering