Bus Blaster v4 Design Overview

Bus Blaster v4 Design Overview

Bus Blaster V4 is a experimental, high-speed JTAG debugger for ARM processors, FPGAs, CPLDs, Flash, and more. Thanks to a reprogrammable buffer, a simple USB update makes Bus Blaster v4 compatible with many different JTAG debugger T Ypes in the popular open source software.

• Based on ft2232h with high-speed USB 2.0
• Buffered interface works with 3.3volt to 1.5volt targets
• Reprogrammable buffer is compatible with multiple debugger types
• Compatible with ' Jtagkey ', ' kt-link ' programmer settings in Openocd, Urjtag, and more
• Should support Serial wire Debug when available
• MINI-CPLD Development board:self programmable, extra CPLD pins to header
• Open Source (CC-BY-SA)

Bus Blaster V4 is a redesign of v3/v2 that supports SWV, an obscure extension to a reduced Pincount JTAG protocol most PEO Ple'll never use. Unless need it, stick with V3 and save a few bucks!

• Can now support the SWV feature of Cortex microcontroller for advance debugging when software support is available
• SWV is little used and does currently supported in software, most users would be better off with Bus Blaster v4 available He Re
• Fitted in a DP9056 (90x56 mm) standard PCB
• Added series resistors to input and output pins to protect against damage and noise

Bus Blaster V4 is available now for $45. Each unit was tested with a real JTAG target before it ships.

Buffer Logic

New buffer logic is designed using simple schematic entry, Verilog, or VHDL, and the free ISE Webpack software from Xilinx .

• See CPLD Development Tutorials

Here is the examples of buffer logic to give the design can is flexible.

• See Bus Blaster buffer logic for the latest buffers and programming instructions

Buffer logic for bus Blaster V4 and Bus Blaster V2/v3 is not compatible!

Jtagkey compatible

Kt-link compatible

Bus Blaster v4 Design Overview