Can three-channel +DDR3 be popularized? Memory change in progress (top)

Memory (memory), as a staging point for coordination between CPU and storage, has been playing an important role in the system. The hardware domain of a number of overall architecture upgrades, and memory has a great relationship, whether it is SDRAM to DDR, and then from DDR to DDR2, as well as the upcoming DDR3, the essence of the upgrade is to improve memory bandwidth, visible memory for the performance of the system has a vital role.

When it comes to memory architecture upgrades, I have to mention Intel, and some people might say, is intel a CPU maker? What's the connection to memory? In the area of hardware, perhaps only Intel is a vendor that can implement new standards for the implementation of hardware devices based on their own development needs. Most of the way, under Intel's leadership, the entire hardware industry is going to follow Intel's footsteps.

Look at our common hardware specifications, from common usb,sata2,pci-e standards, which is not Intel's advocate, today's PC hardware standards are almost all designed by Intel, the other vendors are simply following and production. However, Intel has failed in the specification of memory, perhaps the only failed--DDR memory standard (described below), and since then Intel has not given another chance, DDR2 was promoted under Intel's leadership, and now The memory architecture will open up a new page as the Nehalem that is integrated to support DDR3 memory controllers is about to be released!

CPU Integrated memory controller, is a double-edged sword, although can improve the performance of the system, mainly to reduce system delay, but the frequency of the CPU has become difficult, there are not small manufacturing costs. As a result, the integrated memory controller has always been a question that everyone is happy to discuss, and the pros and cons of it have been debated. Admittedly, when AMD integrates the memory controller and connects the system via the HT bus, it has narrowed the technology gap with Intel.

Nearly 5 years after AMD launched the integrated memory controller, Intel will finally launch the CPU of the integrated memory controller, and in order to suppress the competitor and keep the technology leader's posture, a 3 channel DDR3 is introduced to lead the memory bandwidth to a new height.

According to Intel's information, Nehalem's memory controller is integrated Memory Controller, referred to as IMC. Specifications on the support of three-channel DDR3 memory, the initial maximum support to 1333MHz, but like individual first-line manufacturers of high-end motherboards support OC to 1600MHZ specifications. At the same time, IMC can effectively reduce the delay, and each channel can be run independently, and undoubtedly improve the compatibility problem to some extent. But it is a bit regrettable that Intel does not seem to care for low-end users, and IMC only supports the currently expensive DDR3.

FSB life into the countdown, learn to live in the QPi era

When we are accustomed to the fsb--front-end bus (Front SIDE buses, referred to as FSB), in the face of the arrival of the QPi era, and then talk about the CPU connected to the North Bridge chip bus, QPI will be a new friend, as the replacement of FSB, become the next generation of CPU and CPU, CPU and chipset (CPU and memory) connection between the bus, QuickPath Interconnect (QPI) bus technology, Nehalem into the end of the FSB to promote the death of the messenger.

The key reason for FSB to die, is always fed the memory required bandwidth, even if it is equipped with a strong CPU, the front bus frequency to a new high, users will not obviously feel the overall speed of the computer upgrade. Even the weak phenomX4, also relies on the HT bus technology to narrow its and the Core 2 Yorkfield performance gap, therefore said QPi's birth has the revolutionary significance.

Tip: The current Intel processor mainstream front-end bus frequency of 800MHz, 1066MHz, 1333MHz several, into 2007, Intel in November to the processor front-end bus to 1600MHz (default FSB 400MHz), This is a full boost from the 800MHz FSB bus frequency at the highest end of the 2003. Such a high front-end bus frequency, its bandwidth is how much? When the front bus is 1333MHz, the bandwidth between the processor and the North Bridge is 10.67gb/s, and the elevation to 1600MHz can reach 12.80gb/s, an increase of 20%.

Before testing 3-channel memory performance, I need to introduce the development of memory. DDR memory is the most important memory technology in the last ten years, in the beginning, a legendary version of the technology was almost killed by Intel in the cradle, if not at the peak of the heyday of the company and then the low production process, maybe now we use the memory will not be Ddrx (X=1, 2, 3, 4), It's Rambus and follow-on products.

At the time of the computer system, memory bandwidth is the biggest bottleneck in addition to the hard drive, the chip-level vendors also discuss ways to improve memory performance, one is to Granville as the representative of the old school, one side is to innovate the memory architecture of Intel. The situation was similar to the Hddvd in Blu-ray, but the result was diametrically opposed.

DDR memory in the Acura-Pirate ship XMS