Changes of AARCH64 ARMV8 Neon

• Access to a larger general-purpose register file with unbanked registers (0-30), with each register extended to 64 Bits.

  31 Universal registers, plus one r31 as the zero register.

• floating point and advanced SIMD processing share a register file, in a similar manner to AArch32, but extended to thi Rty-two 128-bit Registers. Smaller registers is no longer packed into larger registers, but is mapped one-to-one to the low-order bits of the 128-b It register

  32 Neon v registers, full length of 128bits, doubled from the previous 16. As a result, the combination of the previous 4x32=2x64=128 is not used. They all exist alone. For example, the S1 of S0 S1 is no longer half the D0.

• Unaligned addresses is permittedfor most loads and stores, including paired register accesses, floating point a nd SIMD registers, with the exception of exclusive and ordered accesses

  Introduction of non-aligned access to paired registers
  

• There is no multiple register LDM, STM, PUSH and POP instructions, but Load-store of a non-contiguous pair of re Gisters is available.

• The A64 instruction set does not include the concept of predicated or conditional execution. Benchmarking shows that modern branch predictors work well enough the predicated execution of instructions does not offer Sufficient benefit to justify their significant use of opcode space, and their implementation cost in advanced implementation S.

  Because the branch predictor is good enough, no branching predictions or conditional execution instructions are available. Strange, the conditional branch jump instruction is not still there? It's not quite understood here.
  

• The first eight registers, R0-R7, is used to pass argument values into a subroutine and to return result V Alues from a function . They may also is used to hold intermediate values within a routine (if, in general, only between subroutine calls)

  The general register parameters are increased from the previous 4 to 7.
  

• The first eight registers, V0-V7, is used to pass argument values into a subroutine and to return result values from a function. They may also is used to the hold intermediate values within a routine (if, in general, only between subroutine calls).

  There are also 7 vector register pass parameters.
  registers v8-v15 must is preserved by a callee acrosssubroutine calls; The remaining registers (V0-V7, v16-v31) does not need to be preserved (or should is preserved by the caller). Additionally, only the bottom 64-bits of each value stored in v8-v15 needto be preserved; It's the responsibility of the caller to preserve larger values.

  V8-v15 must be preserved when a child function is called, but only a low 64bits is preserved.

• Floating point, similar to AArch32 VFP, with some extensions.

Offical Standard Documentation

"1": Procedure call standard for the ARM 64-bit Architecture http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/ Ihi0055b_aapcs64.pdf

If you need the port assembler, you can refer to this

"2": HTTP://WWW.SLIDESHARE.NET/LINAROORG/LCE13-GWGGFXONARMV8

Changes of AARCH64 ARMV8 Neon