Chapter One: SystemVerilog introduction

1. Why to learn SystemVerilog

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2.systemverilog origins

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3.systemverilog Standard Course

systemverilog3.0 for synthesis

systemverilog3.1 for authentication

Systemverilog3.1a

4.systemverilog Key safeguarded

4.1 Interface for encapsulating Communication and protocol checking within the design

4.2 Similar data types in C, such as int

4.3 User-defined type (typedef) enum type, struct, and union

4.4 Type Conversions

4.5package

4.6 External compilation Unit area

4.7++ 、--、 + = Equal assignment operation

4.8 Explicit Process Blocks

4.9priority and Unique modifiers

4.10 Transfer to tasks, functions, and modules by reference

Chapter One: SystemVerilog introduction