Chip encapsulation type image recognition [zz]

From: http://xnian.com/2009/07/1614.html

Encapsulation has gone through the following development processes:

Structure: dip encapsulation (1970s)-> SMT process (1980s lccc/PLCC/SoP/QFP)-> BGA encapsulation (1990s)-> future-oriented process (CSP/mcm)

MATERIALS: metal, ceramics-> ceramics, plastics-> plastics;

Pin shape: Long leads Direct Insertion-> short leads or no-leads mounting-> spherical convex points;

Assembly Method: Through-hole plug-in-> surface assembly-> direct Installation

1. To transistor shape Encapsulation

The Chinese meaning of to (transistor out-line) is "transistor shape ". This is the early encapsulation specification, such as to-92, TO-92L, to-220, to-252 and so on are plug-in encapsulation design. In recent years, the demand for Surface Mount has increased, and to Encapsulation has also progressed to surface mount encapsulation.

To252 and to263 are surface mount packages. Here to-252 is also called D-PAK, to-263 is also called d2pak.

The D-pak Encapsulation has three electrodes, gate (G), drain (d), and source (s ). The pin of the drain pole (d) is not used for cutting, but is directly welded to the PCB using the hot plate on the back as the drain pole (d). On the one hand, it is used to output a large current and Heat Dissipation through the PCB. So there are three PCB D-PAK pad, leakage pole (d) pad larger.

Ii. Dip dual-row direct plug-in Encapsulation

Dip (dualin-line package) is an integrated circuit chip encapsulated in the form of Dual-row direct insertion. Most small-and medium-sized Integrated Circuits (IC) use this encapsulation form, generally, the number of pins cannot exceed 100. Encapsulated materials includePlasticAndCeramics. The CPU chip in dip package has two rows of pins. When used, it needs to be inserted into the chip socket with dip structure. Of course, it can also be directly inserted into the circuit board with the same number of welding holes and geometric arrangement for welding. Dip encapsulation structure:Multi-layer ceramic double row direct dip,Single-layer ceramic double row direct dip,Wire Frame dip(Including glass ceramic sealing Type, Plastic Encapsulation structure, ceramic low-Fused Glass encapsulation type) and so on.

Dip Encapsulation has the followingFeatures:

1. Suitable for Perforation welding on PCB (Printed Circuit Board) for easy operation.

2. Easier PCB wiring than the to package.

3. the ratio between the chip area and the encapsulation area is large, so the size is also large. Taking the CPU with 40 I/O pins in plastic double-row direct-plug-in package (pdip) as an example, the chip area/package area = (3 × 3)/(15.24 × 50) = 1: 86, far from 1. (PS: the ratio of the chip area to the package area is an important indicator to measure whether a chip encapsulation technology is advanced or not. The closer the ratio is to 1, the better. If the package size is far greater than the size of the chip, the package efficiency is very low, occupying a lot of Effective Installation area .)

Purpose:DIP is the most popular plug-in encapsulation. Its application scope includes standard logic IC, memory LSI, and microcomputer circuit. Intel's early CPU, such as 8086 and 80286, used this encapsulation form. cache and early memory chips were also in this encapsulation form.

PS. the following three steps ~ 6. SMT Packaging Technology (surface assembly technology) is used. For more information, see here.

3. QFP rectangular flat Encapsulation

QFP (plastic quad flat pockage) technology achieves a very small distance between CPU chip pins and very fine pins. Generally, large-scale or ultra-large scale integrated circuits use this encapsulation form, the number of pins is generally above 100. The substrate hasCeramics,MetalAndPlasticThree. The center distance of the pin is 1.0, 0.8, 0.65, 0.5, 0.4, 3mm, and other specifications.

ItsFeaturesYes:

1. Use SMT surface installation technology to install and wiring on the PCB.

2. Small package shape size and reduced parasitic parameters, suitable for high-frequency applications. Take the CPU with a center distance of 5mm mm welding zone and a QFP package of 208 I/O pins as an example. If the dimension is 28mm × 28mm, the chip size is 10mm × 10mm, then the chip area/encapsulation area = (10x10)/(28x28) =. 8. Therefore, QFP encapsulation is much smaller than dip encapsulation.

3. Convenient CPU operations and high reliability.

QFPDisadvantagesYes: The Pin is easy to bend when the center distance of the pin is less than 65mm. To prevent pin deformation, several improved QFP varieties are available. Such as encapsulatedBqfp with tree index cushion (see the picture on the right)Gqfp with resin protection ring covering the front end of the pin; set the test Convex Point in the encapsulation body and put it in a special fixture to prevent pin deformation.

Purpose: QFP is not only used for microprocessor (Intel's 80386 processor uses plastic four-sided flat encapsulation), door display and other digital logic LSI circuits, it is also used for analog LSI circuits such as VTR signal processing and audio signal processing.

Iv. SOP small-size packages

The SOP device, also known as soic (small outline Integrated Circuit), is the form of DIP reduction. The center distance of the lead is 1.27mm.PlasticAndCeramics. SOP is also called Sol and DFP. Sop encapsulation standards include SOP-8, SOP-16, SOP-20, and SOP-28. The number behind SOP indicates the number of pins, which is often omitted in the industry, so (small out-line ).

Also derived soj (J-pin small shape package), TSOP (thin and small shape package), VSOP (very small shape package), ssop (small SOP) tssop (thin scale SOP), sot (small shape Transistor), soic (small shape Integrated Circuit), etc.

 

5. PLCC plastic mounting with lead Chip Carrier

Plastic leaded chip carrier (plastic leaded) with a center distance of 1.27mm. The lead is in the J-shape and bent to the bottom of the device. There are two kinds of cables: rectangle and square.

PLCC DeviceFeatures:

1. The assembly area is small, the lead strength is high, and it is not easy to deform.

2. Multiple leads ensure good co-surface and improve the consistency of solder joints.

3. The maintenance is inconvenient because the J-lead is bent down.

Purpose: Most of the BIOS on the Main Board uses this encapsulation form.

Vi. Carrier of lccc unleaded ceramic chip

Lccc (leadless ceramic chip carrier) has two kinds of electrode center distance: 1.0mm and 27mm mm. Usually the number of electrodes is 18 ~ 156.

Features:

1. The parasitic parameters are small, and the noise and delay characteristics are significantly improved.

2. the welding points are prone to cracking due to low stress.

Purpose:It is used for encapsulation of high-speed and high-frequency integrated circuits. It is mainly used for military circuits.

VII. PGA plug-in Grid Array Encapsulation

The PGA (PIN Grid Array package) chip is encapsulated in the form of multiple matrix-shaped pins inside and outside the chip. Each matrix-shaped pin is arranged at a certain distance between the four sides of the chip. The number of pins can be 2-5 circles. During installation, insert the chip into a dedicated PGA outlet. To make it easier for the CPU to be installed and detached, a CPU outlet named zif is available starting from the 486 chip to meet the requirements of CPU installation and disassembly In the PGA package.

Zif (zero inser tion force socket) is a socket with no plugging force. By gently lifting the wrench on the socket, the CPU can be easily and easily inserted into the socket. Then press the wrench back to the original place and use the squeeze pressure generated by the special structure of the socket to firmly connect the CPU pin to the socket. There is no bad contact problem. However, if you need to remove the CPU chip, you only need to gently lift the Wrench of the socket, then the pressure is lifted and the CPU chip can be easily obtained.

The PGA package has the followingFeatures:

1. Easier plugging and high reliability.

2. It can adapt to a higher frequency.

Instance: In intel Series C pu, 80486 and Pentium Pro all adopt this encapsulation form.

8. BGA Ball Grid Array Encapsulation

With the development of integrated circuit technology, the packaging requirements for integrated circuits are more stringent. This is because the encapsulation technology is related to the functionality of the product. When the frequency of the IC exceeds MHz, the traditional encapsulation method may produce the so-called "crosstalk" phenomenon, in addition, when the number of pins of an IC is greater than 208, the traditional encapsulation method is difficult. Therefore, in addition to QFP encapsulation, most of today's high-end chips (such as form chips and chipset) use the BGA (Ball Grid Array P ackage) encapsulation technology.

Purpose:BGA becomes the best choice for high-density, high-performance, multi-pin encapsulation, such as CPU and motherboard chip in the South/North Bridge.

BGA encapsulation technology can be further dividedFive categories:

1. PBGA (plasric bga) substrate:

PBGA is the most common type of BGA encapsulation, and its carrier is a general Printed Board Substrate, such as FR-4. The silicon wafer is connected to the upper surface of the carrier by means of wire press welding, and then molded in plastic form. Some PBGA packages contain cavities, which are called heat-enhanced BGA (ebga. The bottom surface is a partially or completely distributed Solder Ball array with a common component (37pb/63sn). The gap between the solder balls is usually 1.0mm, 1.27mm, and 1.5mm.

PBGA has the followingFeatures:

The carrier is the same as the PCB material, so the thermal expansion coefficient TCE (thermal coefficient of expansion) in the assembly process is almost the same, that is, the thermal matching is good.

Low assembly costs.

The common area is better.

Easy to assemble in batches.

Good electrical performance.

In intel series CPUs, Pentium II, I II, and IV processors all adopt this encapsulation form.

2. CBGA (ceramic bga) substrate:

That is, the ceramic substrate. The electrical connection between the chip and the substrate is usually installed using a flipchip (FC.

Silicon Wafers can be connected to the carrier by means of wire press welding or line face-down of Silicon Wafers by means of flip-chip loading. Then they are encapsulated by filler to protect them. The bottom surface of the ceramic carrier is a 90pb/10sn co-crystal Solder Ball array. The Solder Ball spacing is usually 0mm mm and 1.27mm.

CBGA has the followingFeatures:

Excellent electrical performance and thermal characteristics.

Good sealing performance.

High encapsulation reliability.

Good commonality.

High encapsulation density.

It is not sensitive to moisture because it uses ceramics as the carrier.

Encapsulation costs are high.

The assembly process has poor thermal matching performance and high assembly process requirements.

In intel series CPUs, Pentium I, II, and Pentium Pro processors all use this encapsulation form.

3. FCBGA (filpchipbga) substrate: Hard multilayer substrate.

4. tbga (Tape bga) substrate:The substrate is a one-to-two-layer PCB with soft band.

The tbga array is an extension of the tape automatic bonding technology. The carrier of tbga is the dual-metal band (Carrier Band) of copper/Polyimide/copper ). The copper wires distributed on the surface of the carrier act as transmission, and the copper layer on the lower surface acts as the ground wire. After the silicon wafer and the carrier are connectedSealPlay a protection role. Through holes on the carrier, the upper and lower surfaces are turned on, and the ball array is formed on the through-hole pad using similar wire welding technology. The padding of welding balls is 1.0mm, 1.27mm, and 5mm mm.

Tbga has the followingFeatures:

Encapsulation is light and small.

Good electrical performance.

Heat matching is good during assembly.

Moisture has an impact on its performance.

5. cdpbga (carity do wn PBGA) substrate: it refers to the encapsulation of a square-shaped low-trapped chip area (also known as a cavity area) in the center ).

In summary, BGA encapsulation has the followingFeatures:

1. Although the number of I/O pins increases, the distance between pins is far greater than that of QFP encapsulation, improving the yield rate.

2. Although the power consumption of BGA increases, the electric heating performance can be improved due to the use of the controllable collapse chip Method for welding (C4.

3. The thickness is less than l/2 than that of QFP, and the weight is reduced by more than 3/4.

4. The parasitic parameters are reduced, the signal transmission delay is small, and the adaptive frequency is greatly increased.

5. Assemble common surface welding to greatly improve the reliability.

6. the BGA Package is still the same as QFP and PGA, and occupies a large substrate area.

9. CSP chip size Encapsulation

With the global demand for personalized and lightweight electronic products, packaging technology has improved to CSP (chip size P ackage ). It reduces the size of the chip encapsulation shape, so that the size of the bare chip is as large as that of the package. That is, the side length of the encapsulated IC is no more than 1.2 times that of the chip, and the IC area is no more than 1.4 times larger than that of the grain (die.

CSP encapsulation can be divided into four categories:

1. Lead Frame Type (in the traditional form of Wire Guide), Representative Manufacturers include Fujitsu, Hitachi, Rohm, and Goldstar.

2. Rigid interposer type (hard interpolation board type), Representative Manufacturers include Motorola, Sony, Toshiba, and Panasonic.

3. Flexible interposer type (soft interpolation board type). The most famous among them is tessera's microbga, and CTS's sim-bga adopts the same principle. Other representative vendors include Ge and NEC.

4. wafer Level package (wafer size package): Unlike the traditional single chip packaging method, wlcsp is a single chip that splits the entire wafer into one chip. It is known as the future mainstream of packaging technology, manufacturers that have invested in R & D include FCT, aptos, Casio, epic, Fujitsu, and Mitsubishi Electronics.

CSP Encapsulation has the followingFeatures:

1. meet the increasing requirements of chip I/O pins.

2. the ratio between the chip area and the encapsulation area is very small.

3. greatly shorten the delay time.

CSP packages are suitable for IC with few feet, such as memory stick and portable electronic products. In the future, it will be widely used in information appliance (IA), digital TV (DTV), e-book (e-book), wireless network WLAN/gigabitethemet, ADSL/mobile phone chip, Bluetooth) and other emerging products.

10. MCM multi-chip model mounting

Some people once thought that when a single chip could not reach the integration of multiple chips at the moment, could it make CSP chips with high integration, high performance, and high reliability (using LSI or IC) and dedicated Integrated Circuit Chip (as1c) assembled into a variety of electronic components, subsystems or systems on a high-density multi-layer interconnected substrate using surface Installation Technology (SMT. This idea generates a multi-chip model (MCM ). It will have a significant impact on the modern computer, automation, communications and other fields.

MCM'sFeaturesInclude:

1. The encapsulation delay time is reduced, making it easy to implement high-speed components.

2. Reduce the package size and weight of the machine/component. Generally, the volume is reduced by 1/4, and the weight is reduced by 1/3.

3. The reliability is greatly improved.

Conclusion

ChipSealInstallationThe development is to adapt to the development of micro assembly technology FPT (Fine Pitch technology. Light, thin, small, high I/O number, small shape, small lead or welding ball spacing direction development. With the development of technology, the performance will be further improved, and the price will decrease. In this way, the new era of electronic assembly will come, and the performance of the entire machine will be significantly improved.