Clock Jitter Related concepts

Jitter is defined as the deviation of the signal from its ideal position. This article focuses on clock Jitter and discusses the following types of clock jitter: adjacent periodic jitter, periodic jitter, time interval error (TIE) jitter, phase noise, and phase jitter.

Introduction to Clock Jitter

Clock jitter is the deviation of the clock along the distance from its ideal position. It is important to understand clock jitter in your application because it plays a key role in the system timing budget. It also helps system designers to understand the system timing margin. As system data rates become more and more high, timing jitter has become more critical in system design, such as in some cases where system performance constraints are determined by the system timing margin, so a full understanding of timing jitter becomes more important in system design. Total jitter can be divided into random jitter and deterministic jitter components. This article does not discuss the composition of jitter, but focuses on the different types of clock jitter. Clock timing jitter can be measured in the time domain as well as in the frequency domain. The adjacent periodic jitter, periodic jitter, and time interval error (TIE) jitter are measured in the time domain, while phase noise and phase jitter are measured in the frequency domain. Some jitter sources include thermal noise, power supply noise, ground-bounce noise (ground bounce), Phase-locked loop (PLL) circuitry, crosstalk, and reflection. Figure 1 is an example of clock jitter.

Figure 1: Example of clock jitter

Different types of clock jitter

(1) Adjacent periodic jitter: The clock period change between any 2 adjacent clock cycles in 1,000 clock cycles is measured.

• The RMS of neighboring periodic jitter--measures the deviation of the clock period measurement between any 2 adjacent clock cycles in 1,000 clock cycles.

• Adjacent period Jitter Peak-peak-the difference between the minimum clock period change and the maximum clock period change between any 2 adjacent clock cycles in 1,000 clock cycles is measured.

The adjacent periodic jitter measurement is used to determine the high frequency jitter in the application because it measures jitter between the two adjacent clock cycles. It is important to obtain a smaller cycle-by-period jitter value because it affects the system timing margin.

(2) Periodic jitter: a periodic jitter measurement is the maximum deviation of the clock period of a clock period in 10,000 clock cycle waveforms.

• Periodic jitter RMS – measures the standard deviation of the clock cycle measurements over 10,000 clock cycles.

• Cycle Jitter Peak-to-peak – the difference between the minimum clock period and the maximum clock period measured in 10,000 clock cycles is measured.

The periodic jitter measurement is used to determine the low frequency jitter of the application because it measures jitter by measuring the clock-period deviations in the 10,000 clock cycles. Periodic jitter is used for the calculation of the system timing margin. Figure 2 is an example of a periodic jitter measurement for the Sen-Mei Semiconductor programmable clock nb3n3020.

Figure 2: Example of periodic jitter measurements on semiconductor programmable clock nb3n3020

On Semiconductor's programmable clock nb3n3020 has excellent programmable clock jitter performance, with a typical periodic jitter RMS value of 3 picosecond (PS).

(3) Time interval error (TIE) jitter

The time interval error or tie jitter measures the distance of the clock each working along (active edge) along with the corresponding ideal clock.

* Time interval error (TIE) jitter RMS--standard deviation for measuring timing errors

* Time interval error (TIE) peak-to-peak – the difference between the measurement minimum and the maximum timing error

The time interval error jitter is important for the clock and data Recovery (CDR) PLL, which shows whether the PLL in the CDR can track the influx of quantity flows. A large jitter in the time interval error indicates that the CDR PLL is not able to properly track changes in the influx of data streams. Figure 3 is an example of the on semiconductor nb3n3002 clock generator tie jitter measurement.

Figure 3: Example of the on semiconductor nb3n3002 clock generator tie jitter measurement

(4) Phase noise: Phase noise is measured in the frequency domain, which is the ratio of the signal power to the noise power at the rated 1Hz bandwidth at the given carrier signal migration condition. On Semiconductor's clock products have excellent phase noise performance, such as the nb3n3002/nb3n5573 clock generator with the following phase noise performance:

Offset Noise Power

100hz-103dbc/hz
1khz-118dbc/hz
10khz-122dbc/hz
100khz-130dbc/hz
1mhz-132dbc/hz
10mhz-149dbc/hz

Phase jitter: Phase jitter is measured by the phase noise integral within a specific frequency offset range of the carrier signal. Phase jitter is measured by the amount of energy in a particular frequency offset of the carrier signal that corresponds to the total carrier signal total, and the measurement method is integral to the area under the phase noise graph. For example, the Synchronous Optical Network (SONET) uses a distance carrier signal with a frequency offset of 12kHz to 20MHz, which is integral to the area of the phase noise plot to measure phase jitter. The Fibre Channel (FC) uses a frequency offset of 637KHz to 10MHz from the carrier signal to measure the phase jitter of the area integral under the phase noise graph.

Example of phase noise and phase jitter measurement

The typical phase jitter of on Semiconductor's PureEdge PLL is less than 0.5ps. The phase noise diagram in Figure 4 shows the performance of a PureEdge PLL device NBXDBA018 in the on semiconductor Crystal oscillator product line. This device produces a 155.52mhz/311.04mhz dual-frequency low-voltage forward-emitter-coupled logic (LVPECL) output that meets the jitter requirements of SONET applications.

Figure 4: Phase noise diagram showing typical phase jitter of on semiconductor PureEdge PLL less than 0.5ps

Summarize:

This article describes clock Jitter and illustrates the different types of clock jitter and the significance of various types of clock jitter measurements. This paper also gives an example of different types of clock jitter measurements. As system data rates increase, sometimes system performance constraints are determined by the system timing margin, so understanding timing clock jitter is important for system designers.

Clock Jitter Related concepts