Clock PIN setup issues Xilinx error:place:864-incompatible IOB ' s is locked to the same bank 0

ERROR:PLACE:1108-A clock Iob/bufgmux Clock component pair have been found
That is not a placed at a optimal clock Iob/bufgmux site pair. The clock
IOB component <Clk_125M> is placed at site <pad99>. The corresponding BUFG
Component <U_Clk_ctrl/U_2_CLK_SWITCH/U_BUFGMUX> is placed at site
<bufgmux_x2y12>. There is only a select set of Iobs. can use the fast
Path to the Clocker buffer, and they is not being used. Want to
Analyze why this problem exists and correct it. If this sub optimal condition
is acceptable for this design, the Clock_dedicated_route
Constraint in the. UCF file to demote this message to a WARNING and allow
Your design to continue. However, the use of this override is highly
Discouraged as it may leads to very poor timing results. It is recommended
That this error condition is corrected in the design. A List of all the
COMP. PINs used in this clock placement the rule is listed below. These examples
Can is used directly in the. UCF file to override this clock rule.
< NET "clk_125m" clock_dedicated_route = FALSE; >

You add this phrase under your PIN statement NET "CP" Clock_dedicated_route = FALSE; Because this is the result of a timing constraint.
The final look is the following:
NET "I_CLK" clock_dedicated_route = FALSE;
NET "I_CLK" LOC = B18;

Ise compile-time error encountered, there are many such instructions on the Internet

Error:place:1018-a Clock Iob/clock component pair has been found that is not placed at an optimal clock IOB/
Clock site pair. The clock component <in_BUFGP/BUFG> is placed at site <bufgmux_x2y10>. The IO component <in> is
placed at site <pad60>. This won't allow the use of the fast path between the IO and the Clock buffer. If this
Sub optimal condition is acceptable for this design, the Clock_dedicated_route constraint in the. UCF
File to demote the message to a WARNING and allow your design to continue. However, the use of this override is
Highly discouraged as it may leads to very poor timing results. It is recommended the This error condition be
Corrected in the design. A List of all the COMP. PINs used in this clock placement the rule is listed below. These
Examples can used directly in the. UCF file to override this clock rule.
< NET "in" Clock_dedicated_route = FALSE; >
This error can be omitted from the previous version of Ise by adding an environment variable, which can be added to the UCF file in Ise12:

NET "in" Clock_dedicated_route = FALSE;

to ignore this error, the error may be caused by:

When the clock is connected to the FPGA differential clock of the n feet, the single-ended clock must be connected to the P-pin, in order to use the global clock cabling resources to ensure clock performance.

Clock PIN setup issues Xilinx error:place:864-incompatible IOB ' s is locked to the same bank 0