Cloud6410 interrupt and External Interrupt

6410 of system interruptions:

In addition to interrupt initialization, interrupt processing in embedded software is mainly used to write ISR.
 
In the CPU of the embedded SoC, some device modules are embedded in the CPU. The interruptions they produce are called internal interruptions. Because the cabling is relatively fixed, programming is relatively simple. In addition, the interrupt caused by the chip physically separated by CPU is called an External Interrupt. The External Interrupt can be connected to different interrupt feet. Therefore, it is necessary to perform complicated configuration for the interrupt Io.
 
Is the round robin mode useless?The advantage of round-robin is that, under heavy loads, round-robin is much more efficient than interruption.For example, when many students keep asking questions in a classroom, instead of being interrupted, it is better for the teacher to get up and walk around in the classroom, and the random handling of student problems will be much higher.
 
 
Exception)
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Exception (exception) in the computer architecture, exceptions or interruptions are a mechanism for handling emergencies in the system. Almost all processors provide this mechanism. Exceptions are mainly described from the perspective of passive processor acceptance, which refers to exceptions caused by accidental operations. However, interruption means an active application to the processor. However, these two cases share a certain degree of commonality. They are a mechanism in which the request processor interrupts the normal Program Execution Process and enters a specific program.

From the perspective of structure, the interruption caused by external devices can be considered as a special exception. In addition to the interruption, there are also many fixed exceptions in arm, including the following seven types:

1. Reset (reset)

When you press the reset key, a reset exception occurs. At this time, the program jumps to the reset exception handler and runs it. When the CPU restarts, the reset exception occurs.

2. undefined commands

When an ARM processor or coprocessor encounters a command that cannot be processed, an undefined command exception occurs. Using this mechanism, the arm or thumb instruction set can be extended through software simulation.

3. software interruption (SWI)

Hardware interruption is caused by a fixed hardware interruption, which means that no specific hardware is generated and is virtualized by the CPU. This exception is generated by SWI executed by the program. The advantage of soft interruption is,

It can be used by programs in user mode to call privileged operation commands. Linux system calls are implemented using this exception.

Optimization of program structure is available. for example, in a Linux driver, hardware interruption cannot be performed for a long time. however, the long-term operations of many software depend on interrupted calls. sometimes, in order to solve this conflict, there will be two levels of Driver Design, namely hardware interruption from hardware access, and simulation of software interruption for long operation.

4. Command prefetch aborted

If the address of the prefetch instruction does not exist or the address does not allow access to the current instruction, the memory will send a stop signal to the processor. However, when the prefetch instruction is executed, the command prefetch is aborted. for example, you can use ads to download the program to the 0x8000 address on the Development Board. an Abort exception occurs.

5. Data Suspension

If the processor data access address does not exist or the address does not allow access by the current command, an exception occurs.

6. IRQ

An IRQ interrupt is triggered when an external device generates an interrupt signal on an external interrupt pin. This is the most common method used by an external device.

The s3c24x0 is an Integrated SOC, except for the arm module. other internal integration modules, such as USB, RTC, etc. these modules will also be disconnected to the ARM920T kernel within the CPU. however, these pins are invisible outside the CPU and can only be used for register control.

Some gpio feet act as the control line of external interruption, and the external IC can connect its own interrupt signal line to the corresponding interrupt foot. when the external production interruption signal, the CPU can know that there is a peripheral interruption.

7. FIQ

Fast interruption, similar to IRQ, but with fast response speed and strict conditions set as FIQ. For example, one FIQ can only be triggered at a time.

 

In a word, interruption (IRQ, Fiq, SWI) is a special exception. When an external interrupt occurs, most CPUs only generate one exception. In the exception handling program, the software reads different interrupt Register Analysis and then calls ISR. Here ISR is executed by software. This is the mechanism like S3C2440.

A simplified interrupt handling process can also be used in. The CPU directly calls the interrupted ISR for processing. In this way, the difficulty of writing Interrupt Processing Software is greatly reduced.

 

 

Vector)

The address of the exception handling function or interrupt processing function is arranged in a continuous memory in the order of the interrupt number. From the perspective of C language, it can be seen as a pointer array. An array is also called a vector ).

If you are familiar with the Interrupt Processing Mechanism of S3C2440, you can find that the process of interrupt programming is much simpler than that of s36410.
 
 
Compared with the detailed and rich explanations about the interrupt in the S3C2440, The Datasheet of the s36410 is obviously a rush. There are only 15 pages of the interrupt, and a large amount of content is still a register table.
 
Therefore, most of the following I have pushed back from the testing program of the and application note. And re-use the ads Write Program for verification.
 

 
The main improvement of the interruption of the is.
 
The interrupt vector controller is added. In this way, the interrupt processing mechanism that is redirected by software is needed in the S3C2440. In this way, the hardware is used to redirect the module in the s36410. You only need to store the ISR address in the continuous vector register space, rather than manually managing the space allocated by yourself like S3C2440.
 
In other words, an IRQ/FIQ exception is triggered by the CPU in the S3C2440, and the relevant interrupt register is searched in the exception handling function to jump to the specified ISR, however, all of them can be automatically processed by the VIC hardware. This greatly simplifies Interrupt Processing programming.
 
The other is that the external interrupt is added to the filter circuit. In this way, hardware can be used for filtering where the original software glitch is needed, which greatly simplifies the External Interrupt Processing.

Operation interrupted by cloud6410
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Interrupt No.

64 interrupts are divided into vic0 and vic1 groups by hardware group. Each group is processed by a corresponding register.
The interrupt number 0-31 is the vic0 group.
The interrupt number is 32-63 and is in the vic1 group.
 
It is very easy to interrupt the operation on the cloud6410.
 
Enable vicxintenable
The value 0, 1, 0, 31 indicates that vic0intenable is used for interruption, and indicates that vic1intenable is used for interruption. the following registers are the same and will not be repeated.
 
The corresponding bit is 1, indicating that the interrupt is available. For example, if the No. 0 interrupt is valid, the 0th bit of vic0intenable is 1.

Disable an interruption
To the position 1 corresponding to vicxintenclear, this interrupt is disabled.

Set the interrupt type
Set whether an interrupt is IRQ or FIQ. Note that only one interrupt can be FIQ. Set the corresponding bit 1 to FIQ.

Set the vector address (ISR address) of the number)
Note that the 32 consecutive registers are generated as two register arrays in. The first addresses are 0x71200100 and 0x71300100. you can operate on them like a pointer array. The subscript of the array is the interrupt number. Each interrupt source corresponds to its own interrupt address bit. There are 64 interrupt sources in total, so it is two 32*32 arrays.
This setting greatly simplifies the vector organization of Isr.

Set interrupt priority
This also uses 32*2 registers to form two priority arrays. Each register has a priority value ranging from 0 to 15.

Indication after interruption
Because of the use of Vic, many srcpnd, intpnd, effecffset, and subsrcpnd registers are saved. The current ISR address is directly indicated by vicxaddress.
 

 
Note that the vicxaddress register is called in system bus. Call in. This method is not recommended, because this mode is equivalent to using software for ISR jump of S3C2440.
The reference process provided by Samsung.

The more simple call method is the vic port mode, which is strongly recommended by me. After the system is interrupted, the VIC will directly execute the corresponding ISR. This is not just simple programming, but it is more efficient because it does not have access to vicxaddress and execution time on system bus.
To use this mode, you only need to add specific code at startup.

External Interrupt Programming

In addition to the INT_EINT0-INT_EINT4, all interruptions are triggered by the internal module of. It is called an internal interrupt.

The INT_EINT0-INT_EINT4 is an external interrupt, which is triggered by peripherals outside the CPU. which interrupt is triggered depends on which gpio interrupt pin the peripheral is connected.
Network controllers and buttons of the Development Board are all mounted on some gpio. They all use a typical external interrupt.
 
External Interrupt pin
Groups of gpio ports to act as external interrupt ports
Group 0th, total 28 feet. GPN0-GPN15 (16 feet), GPL8-GPL14 (7 feet), GPM0-GPM4 (5 feet)
1st groups, by the GPA0-GPA7, 8 medium broken feet, GPB0-GPB7, 8 medium broken feet
2nd groups, by the GPC0-GPC0, a total of 8 out of the foot...
...
8th groups, by the GPP0-GPP14, a total of 15
9th groups, by the GPQ0-GPQ8, a total of 9 out of the feet
 
External Interrupt number
 
Devices with 0th to 0th feet in the 3rd group will trigger int_eint0 = 0 interruption
Step 4-11 of group 0th will trigger int_eint1 = 1 interruption
The 12-19 leg of the 0th group will trigger int_eint2 = 32 interrupt
The 20-27 feet in The 0th group will trigger int_eint3 = 33 interruption
1st group-9th All groups of devices only trigger int_eint4 = 53 interruption
 
We can see that each group shares an interrupt number with multiple broken feet. Among them, 0th groups are commonly used, occupying three interrupt numbers, and each pin has its own sub-interrupt. 1-9 groups share an interrupt number, with each group having a sub-interrupt source.

In ISR, how does one determine which interrupt occurs?
 
How does the software know which device causes the same interruption?
Determined by External Interrupt pending register

The 0th group is determined by eint0pend. The corresponding foot position can be referenced, which is not very regular.

Group 1 and 2 are determined by eint12pend.

And so on, eint34pend, eint56pend, till eint9pend to indicate

External Interrupt signal type
 
Set the signal generated by the interruption to be captured. There are five main types: low level, high level, rising edge, falling edge or both,
The 0th group uses two registers, eint0con0 and eint0con1.
 

 
Group 1 and 2 Use eint12con,
Group 3 and 4 Use eint34con,
And so on

Temporarily disable External interruption
The eintxmask is a temporary shutdown interrupt.
If it is set to 1, an interruption is disabled. If it is set to 0, it is opened only when the interruption is used.

Eint0mask is used in 0th groups

The eint12mask is the Interrupt Mask of group 1 and 2.

And so on...

Define hardware filter types

Some External Interrupt signals with irregular waveforms can be normalized through the filter circuit, which simplifies software writing.

Two filter circuits are available in the S, one is latency filtering (such as button interruption can be used), the other is digital sampling filtering, and the other is sampling width.

The eint0fltcon0, eint0fltcon1, eint0fltcon2, and eint0fltcon3 configurations are used for filtering in The 0th group.

Flten indicates whether the filtering function is enabled, fltsel indicates the filtering method, and eintn indicates the width of digital filtering.

Group 1 and 2 are filtered using eint12fltcon.
Eint34fltcon is used for filtering group 3 and 4.

Eint9fltcon is used for group filtering.

External Interrupt Programming
 
Apart from interrupting all programming processes,
Generally, the corresponding gpxcon is configured as a medium pin.
The filter mode and interrupt signal mode are also configured.
 

Enable the External Interrupt Mask.
 
In ISR, in addition to clearing the vicxaddress 0, the corresponding vicxsoftintclear bit is also required.
 
Software interrupt programming
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There are 64 soft disconnections (corresponding to hardware disconnections) in the, Which is vague. Can a hardware interrupt be triggered by software or is there a completely corresponding software interrupt? This requires software verification.
 
In addition to the hardware interruption, the Soft Interrupt process must include the following two items.
Use vicxsoftint to trigger Soft Interrupt
Use vicxsoftintclear when ISR exits

Soft Interrupt Programming process