Comparison between ARM and MIPS (X86)

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1. Pipeline StructurePipeline
-MIPS is one of the simplest architectures, so the university prefers to choose MIPS architecture to introduce the computing architecture course.
-ARM has barrel shifter
Shifter has two sides. On the one hand, it can improve the speed of mathematical logic operations, and on the other hand, it also increases the complexity of hardware. Therefore, it is more efficient than adder/shift register that can accomplish the same function, but it also occupies more chip area.

-MIPS have "branch delay slot" and "load delay slot"
MIPS uses the compiler to solve the above two problems. Because MIPS was originally designed to use simple RISC hardware, and then rely on compilers and other software technologies to achieve the complete concept of the MIPS.

2. Command StructureInstruction
-MIPS have 32bit and 64bit architecture, but ARM only have 32bit architecture
ARM11 local 64-bit
-MIPS is an open architecture. You can add your own commands to the developed kernel,
-ARM has 4-bit condition code in every instruction
ARM is like x86 at this point. MIPS also adds the "conditional move" command to mips iv to improve the pipeline efficiency.
-ARM has pre-and post-increment addressing modes
Auto-increment/decrement on load/store instructions
-In terms of saving code space, MIPS16 is similar to ARM Thumb.

3. RegistersRegister
-Because there are 32 registers in the MIPS kernel, and there are only 16 registers in ARM, the inherent advantages of this structure design determine the same performance, the chip area and power consumption of MIPS are smaller.
-ARM has a set of special purpose register cp0-cp15, can use MCR, MRC and other command control; correspondingly, MIPS also has cp0 0-30, use mfc0, mtc0 Command Control.

-Register banking in ARM. r8-r12 FIQ mode; r13: SP r14 R
I don't feel any benefit from banked register.

-MIPS has a hard-wired-to-zero register, but ARM not
MIPS use register $0 for Zero

4. Address SpaceAddress space
-The starting address of MIPS is 0xbfc00000, which has a size limit of 4 Mbyte. However, generally, MIPS chips adopt some methods to solve this problem.
ARM does not have this problem.
The starting address of MIPS24K is changed to 0xbf000000, and now there is 16 Mbyte space.

-MIPS don't have to turn paging on to enable the cache.
MIPS have the address space for both cache and un-cache
But ARM need enable/disable cache

5. FunctionsFunction
-Float point: MIPS64 has.
ARM's support for FP is limited, and usually not supported ded, and it is a 32 bit architecture
-ARM use JTAG and MIPS use EJTAG. Both Debug tools are supported. The usage is similar.

6. PerformancePerformance
-Performance Comparison: It is difficult to tell who is better or worse because of the large difference. In my personal experience, the performance of mips4 K is basically the same level as that of ARM9. however, the performance of arm4.
Similarly, the performance of the 32bit MIPS24K is much higher than that of the MIPS4K, and it should be better than that of the ARM9.
Because we have never used ARM11 or MIPS34K chips, we can't compare them, but it seems that these two chips are of the same level.

7. Application
-For applications above MHz, it is difficult to find products using ARM architecture.
The MIPS architecture is rarely used in MHz or below MHz, which is precisely the main market of ARM.
-ARM is used in mobile phones and other portable fields. MIPS is used in residential gateways, cable modems, and cable set-top boxes.
-ARM uses hard core authorization; MIPS uses soft core authorization. You can configure it as your own product.

8. Future Development
-The next generation of ARM goes towards a multi-core structure, while the next-generation core of MIPS is switched to the hardware multi-thread function (multithreading)
MIPS multithreading is similar to Intel's HyperThreading technology. From the current development perspective, multiple kernels have the upper hand.

 

 

 

 

 

Http://ydragongfly.blog.sohu.com/116425075.htm

 

1. Differences between MIPS and X86 TLB

This is the processing of TLB Miss:

MIPS triggers a TLB Refill exception. The kernel's tlb_refill_handler uses pgd_current as the PGD base address of the current process. The index obtains the PTE corresponding to the failed virtual address and fills it in TLB, after the CPU completes, the virtual address that failed to be converted should be taken to TLB.

When tls B is not hit, X86 uses the hardware MMU as the base address of PGD of the current process. After the index obtains the PFN, it directly outputs the PA. At the same time, MMU fills in TLB to speed up the next conversion.

In addition, if the conversion fails, MIPS is stored using the BadVAddr register, and X86 is stored using CR2.

2. about the size of the page table of MIPS32, the kernel will call _ get_free_pages to allocate a page to the page Directory table for every fork process or clone process without the CLONE_VM flag, the first 512 initialization items all point to invalid_pte_table (empty page table, total PAGE_SIZE/sizeof (pte_t) items), and the subsequent items are inherited from the init process. Then, the kernel allocates a page table (size as one page) for the new process based on the storage space required by the new process, allocates a memory page, and sets the corresponding page table items, set the corresponding page Directory table items.

As you can see, as long as the number of processes is fixed, the space required for the page Directory table is fixed, and each process page Directory table is a page size; the total page table size of a process depends on the Process Code and data size.

In a typical MIPS32 system, the page size is 4 kb. in single-user mode, only bash processes exist. The page table size is about 48 KB (cat/proc/meminfo | grep PageTables ); the page Directory size can be calculated as follows:

PGD_SIZE = NR_PROCESS (exclude kernel thread) * PAGE_SIZE

3. The main data of each item of mips tlb is: | G | ASID | VPN | PFN |, where VPN is virtual page number and PFN is physical frame number. There is no order between items, and the CPU conversion directly matches. It cannot be called a Page Table.

When the Page Table was designed as an array structure, the subscript of the array as the virtual Page number was taken into consideration. Even today, we can still understand its ingenuity.

4. When the kernel jumps from the assembly language to the C language, where is the top of its stack set?

Before entering start_kernel, the kernel points esp to init_thread_union + THREAD_SIZE. init_thread_union is located in the. data. init_task section. It is a union structure and its size is THREAD_SIZE. The definition is clever:

Union thread_union {
Struct thread_info;
Unsigned long stack [thread_size/sizeof (long)];
};

5. kernel-state threads, kernel threads, and kernel stack of processes

The implementation of the thread library in Linux is based on commonly used linuxthread or nptl. These Library Creation threads use these flags clone_vm | clone_fs | clone_files | clone_sighand to call clone, is a lightweight process.

When the fork, vfork, and clone functions are used to create processes or lightweight processes, the kernel will call alloc_task_struct () to allocate a task_struct to it; call alloc_thread_info (). On the surface, it is optimistic that the thread_info structure is allocated, actually:

# Define alloc_thread_info (TSK) kmalloc (thread_size, gfp_kernel)

The space allocated with thread_size is thread_info at the bottom, and the pointer to it is stored in task_struct-> thread_info. We can see that task_struct-> thread_info + thread_size is the kernel stack bottom of the process or lightweight process.

Whether using clone to generate a lightweight process or using kernel_thread to create a kernel thread, they all enter do_fork and call alloc_thread_info (). Therefore, they all have a kernel stack with the size of thread_size, the bottom is thread_info.

Therefore, in Linux, each thread has a kernel stack, which is a problem when the number of threads is large.